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* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]] | * [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]] | ||
* [[Convey PDK Tutorial]] | * [[Convey PDK Tutorial]] | ||
* [[Media:Tutorial2.pdf | Convey Floating Point Addition Tutorial (.pdf)]] | |||
* [[Test Benches | Use Test Benches to test components of your Personality]] | |||
* [[Using the Memory Controller Interface]] | * [[Using the Memory Controller Interface]] | ||
* [[Running the Vector Adder Example Application]] | * [[Running the Vector Adder Example Application]] | ||
| Line 20: | Line 22: | ||
* [[Using GPROF]] | * [[Using GPROF]] | ||
* [[Convey vector example | Example of Loop Unrolling using FPGA]] | * [[Convey vector example | Example of Loop Unrolling using FPGA]] | ||
* '''[[Frequently Asked Questions]]''' | |||
== Projects == | |||
* [[Ideas Page | Project Ideas Page]] | |||
* [[Sobel Algorithm | Speeding up Sobel Algorithm]] | * [[Sobel Algorithm | Speeding up Sobel Algorithm]] | ||
== Reference Manuals == | == Reference Manuals == | ||
| Line 74: | Line 80: | ||
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]] | *[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]] | ||
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]] | *[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]] | ||
== Spring 2013 Teams == | |||
* [[Team Cyc05]] | |||
* [[Team Challenger]] | |||
* [[Team Blitz]] | |||
== Spring 2012 Teams == | == Spring 2012 Teams == | ||
| Line 79: | Line 90: | ||
* [[Team Slytherin]] | * [[Team Slytherin]] | ||
* [[Team 142857]] | * [[Team 142857]] | ||
Latest revision as of 03:43, 13 May 2013
Articles
Convey HC-1 Tutorials
- Connecting to convey-1.ece.iastate.edu
- Setting Up Environment Variables on Convey's HC-1
- Convey PDK Tutorial
- Convey Floating Point Addition Tutorial (.pdf)
- Use Test Benches to test components of your Personality
- Using the Memory Controller Interface
- Running the Vector Adder Example Application
- Analyze the Simpleton Basic App
- Create a Custom Bitfile
- Using a Custom Bitfile in C Code
- Adding VHDL Files to a Project
- The Verilog Hardware Interface for CAE
- Using ISE's Core Generator to build FIFOs and other IP cores
- Projects with Multiple Bitfiles
- Using the Write-Complete Interface
- Using the Timing Analyzer
Projects
Reference Manuals
Convey
- Convey PDK Reference Manual (.pdf) (updated to V5.2; April 2012)
- Convey Programmers Guide (.pdf) (updated to V1.8; November 2010)
- Convey Reference Manual (.pdf)
- Convey SPAT (Simulator Performance Analysis Tool) Guide
- Convey PDK (.pdf)
- Convey Overview (.pdf)
The newet version of these documents are available at Convey's Support Site
CUDA
Links
- www.asic-world.com - Great Tutorials for those Learning HDLs
- MemoCODE 2012
Other Articles
Helpful Guides
- Modelsim and ISE
- The Verilog Golden Reference
- "The Shock and Awe" VHDL Tutorial
- Verilog vs. VHDL
- VHDL Simple Code Examples
- VHDL Primer
- Using VHDL components in Verilog
- Modelsim Users Guide
- Useful Modelsim Commands
- Installing CUDA on Ubuntu
- General Purpose Computation on GPUs (GPGPU)
- Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [1]
- Guide to Remote Connecting