Test Benches

Overview

Nobody likes waiting 6 minutes for Convey's hardware simulator to finish in order to see the result of a small change of code. By writing a test bench, you can be looking at waveforms in a few seconds.

Tutorial

1. Open Xilinx's ISE from the terminal (make sure your environmental variables are set):

ise &

1. Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
2. Add the DUT (DUT = device under test; i.e. the verilog file)
3. Create a new testbench file (example below)
4. Simulate

/*
Basics of any testbench:
 - create reg's for all inputs to the DUT (device under test)
 - create wires for all the outputs of the DUT
 - use an initial block to send the DUT stimulus
 
According to software, correct output of simulation 
should be (seed=0, size=32, exact=1):
hash(0)  = 2;
hash(10) = 12;
hash(20) = 4;
hash(30) = 19;
*/
`timescale 1ns / 1ps
module hash_tb();

reg clock, reset;
reg stall, exact_match;
reg [199:0] key;
reg [31:0]  seed, table_size;
reg [1:0]   control;

wire [199:0] key_out;
wire [31:0]  index;
wire [1:0]   control_out;

always
begin
	#1 clock <= 0;
	#1 clock <= 1;
end

hash dut(
    // Inputs
    .rst(reset),
    .clk(clock),
    .stall(stall),
    .key(key),
    .seed(seed),
    .table_size(table_size),
    .ctr_in(control),
    .exact_match(exact_match),
    // Outputs
    .key_out(key_out),
    .table_index(index),
    .ctr_out(control_out)
);

initial
begin
	reset <= 1;
	stall <= 1;
	key   <= 0;
	seed  <= 0;
	table_size <= 32;
	control <= 3;
	exact_match <= 1;
	
	#50
	
	reset <= 0;
	stall <= 1;
	key   <= 0;
	
	#100
	
	stall <= 0;
	key   <= 200'h0123456789ABCDEF0123456789ABCDEF;

	#100
	
	key <= 0;
	
	#100
	
	key <= 10;
	control <= 0;
	
	#100
	
	key <= 20;
	
	#100
	
	key <= 30;
	control <= 0;
	
end

endmodule