Main Page: Difference between revisions
Jump to navigation
Jump to search
| (18 intermediate revisions by 7 users not shown) | |||
| Line 3: | Line 3: | ||
* [[Connecting to convey-1.ece.iastate.edu]] | * [[Connecting to convey-1.ece.iastate.edu]] | ||
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]] | * [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]] | ||
* [[Convey PDK Tutorial]] | |||
* [[Media:Tutorial2.pdf | Convey Floating Point Addition Tutorial (.pdf)]] | |||
* [[Test Benches | Use Test Benches to test components of your Personality]] | |||
* [[Using the Memory Controller Interface]] | |||
* [[Running the Vector Adder Example Application]] | * [[Running the Vector Adder Example Application]] | ||
* Convey pdk tutorial: [[image:ConveyTutorial1.pdf]] (uses newCnyProject script) | <!-- * Convey pdk tutorial: [[image:ConveyTutorial1.pdf]] (uses newCnyProject script) --> | ||
* [[Analyze the Simpleton Basic App]] | * [[Analyze the Simpleton Basic App]] | ||
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]] | * [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]] | ||
| Line 18: | Line 22: | ||
* [[Using GPROF]] | * [[Using GPROF]] | ||
* [[Convey vector example | Example of Loop Unrolling using FPGA]] | * [[Convey vector example | Example of Loop Unrolling using FPGA]] | ||
* '''[[Frequently Asked Questions]]''' | |||
== Projects == | |||
* [[Ideas Page | Project Ideas Page]] | |||
* [[Sobel Algorithm | Speeding up Sobel Algorithm]] | * [[Sobel Algorithm | Speeding up Sobel Algorithm]] | ||
| Line 57: | Line 66: | ||
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference] | * [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference] | ||
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial] | * [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf "The Shock and Awe" VHDL Tutorial] | ||
* [http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL] | |||
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples] | * [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples] | ||
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer] | * [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer] | ||
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog] | * [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog] | ||
* [[Modelsim Users | * [[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]] | ||
* [[Useful Modelsim Commands]] | * [[Useful Modelsim Commands]] | ||
* [http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu] | |||
* [http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)] | |||
* Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf] | |||
* [[Media:Connect_Remotely_Via_VPN.pdf | Guide to Remote Connecting]] | |||
== Readings for Memocode 2012 == | == Readings for Memocode 2012 == | ||
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]] | *[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]] | ||
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]] | *[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]] | ||
== Spring 2013 Teams == | |||
* [[Team Cyc05]] | |||
* [[Team Challenger]] | |||
* [[Team Blitz]] | |||
== Spring 2012 Teams == | == Spring 2012 Teams == | ||
| Line 71: | Line 90: | ||
* [[Team Slytherin]] | * [[Team Slytherin]] | ||
* [[Team 142857]] | * [[Team 142857]] | ||
Latest revision as of 03:43, 13 May 2013
Articles
Convey HC-1 Tutorials
- Connecting to convey-1.ece.iastate.edu
- Setting Up Environment Variables on Convey's HC-1
- Convey PDK Tutorial
- Convey Floating Point Addition Tutorial (.pdf)
- Use Test Benches to test components of your Personality
- Using the Memory Controller Interface
- Running the Vector Adder Example Application
- Analyze the Simpleton Basic App
- Create a Custom Bitfile
- Using a Custom Bitfile in C Code
- Adding VHDL Files to a Project
- The Verilog Hardware Interface for CAE
- Using ISE's Core Generator to build FIFOs and other IP cores
- Projects with Multiple Bitfiles
- Using the Write-Complete Interface
- Using the Timing Analyzer
Projects
Reference Manuals
Convey
- Convey PDK Reference Manual (.pdf) (updated to V5.2; April 2012)
- Convey Programmers Guide (.pdf) (updated to V1.8; November 2010)
- Convey Reference Manual (.pdf)
- Convey SPAT (Simulator Performance Analysis Tool) Guide
- Convey PDK (.pdf)
- Convey Overview (.pdf)
The newet version of these documents are available at Convey's Support Site
CUDA
Links
- www.asic-world.com - Great Tutorials for those Learning HDLs
- MemoCODE 2012
Other Articles
Helpful Guides
- Modelsim and ISE
- The Verilog Golden Reference
- "The Shock and Awe" VHDL Tutorial
- Verilog vs. VHDL
- VHDL Simple Code Examples
- VHDL Primer
- Using VHDL components in Verilog
- Modelsim Users Guide
- Useful Modelsim Commands
- Installing CUDA on Ubuntu
- General Purpose Computation on GPUs (GPGPU)
- Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [1]
- Guide to Remote Connecting