User contributions for Cnel711
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20 February 2013
- 01:2201:22, 20 February 2013 diff hist +27 Analyze the Simpleton Basic App →Overview current
- 00:5600:56, 20 February 2013 diff hist +1,872 N Test Benches New page: == Overview == Nobody likes waiting 6 minutes for Convey's hardware simulator to finish in order to see the result of a small change of code. By writing a test bench, you can be looking a... current
- 00:4900:49, 20 February 2013 diff hist +77 Main Page →Convey HC-1 Tutorials
- 00:4200:42, 20 February 2013 diff hist +127 Analyze the Simpleton Basic App →Download
- 00:3300:33, 20 February 2013 diff hist +63 Analyze the Simpleton Basic App →Overview
- 00:2800:28, 20 February 2013 diff hist +683 Analyze the Simpleton Basic App No edit summary
- 00:1400:14, 20 February 2013 diff hist +8 Analyze the Simpleton Basic App No edit summary
18 February 2013
- 18:1118:11, 18 February 2013 diff hist +1 Adding VHDL Files to a Project →Instantiation in Verilog current
4 February 2013
- 21:3521:35, 4 February 2013 diff hist +935 Frequently Asked Questions →How to run Modelsim GUI while simulating?
5 December 2012
- 14:5814:58, 5 December 2012 diff hist +89 Using the Timing Analyzer →Q. I know what module is causing timing issues... how can I just get timing data on 1 module instead of building the entire bitfile? current
4 December 2012
- 19:1119:11, 4 December 2012 diff hist +823 Using the Timing Analyzer No edit summary
29 November 2012
- 20:0420:04, 29 November 2012 diff hist +32 Using the Timing Analyzer →Other Advice
- 20:0320:03, 29 November 2012 diff hist +66 Using the Timing Analyzer →Q. I know what module is causing timing issues... how can I just get timing data on 1 module instead of building the entire bitfile?
- 20:0120:01, 29 November 2012 diff hist +303 Running the Vector Adder Example Application →Interactive Mode for ModelSim Simulation
- 19:5919:59, 29 November 2012 diff hist +47 Tutorial: Creating a Custom Bitfile →Choose a New Signature
- 19:5819:58, 29 November 2012 diff hist +43 Tutorial: Creating a Custom Bitfile →FPGA Usage Statistics
8 November 2012
- 18:1518:15, 8 November 2012 diff hist −57 Main Page →Convey
- 00:3200:32, 8 November 2012 diff hist +95 Main Page →Helpful Guides
6 November 2012
- 16:0116:01, 6 November 2012 diff hist +543 Using the Timing Analyzer No edit summary
- 02:0802:08, 6 November 2012 diff hist +54 Using ISE's Core Generator to build FIFOs and other IP cores →Why Use Dedicated Logic
- 02:0102:01, 6 November 2012 diff hist +1,007 Using ISE's Core Generator to build FIFOs and other IP cores No edit summary
4 November 2012
- 04:2004:20, 4 November 2012 diff hist +21 Main Page →Links
- 04:2004:20, 4 November 2012 diff hist +70 Main Page →Links
2 November 2012
- 18:4618:46, 2 November 2012 diff hist +244 Using the Timing Analyzer No edit summary
1 November 2012
- 22:0622:06, 1 November 2012 diff hist −57 Running the Vector Adder Example Application →Interactive Mode for ModelSim Simulation
- 22:0022:00, 1 November 2012 diff hist +127 Running the Vector Adder Example Application →Interactive Mode for ModelSim Simulation
- 21:0321:03, 1 November 2012 diff hist +94 Using the Timing Analyzer →Q. How do I know what's Causing the Timing Issue
- 05:2505:25, 1 November 2012 diff hist +32 Using the Timing Analyzer →Q. How do I know what's Causing the Timing Issue
- 05:1105:11, 1 November 2012 diff hist +46 Using the Timing Analyzer No edit summary
- 01:5201:52, 1 November 2012 diff hist +3 Using the Timing Analyzer →How do I know what's Causing the Timing Issue
- 01:5201:52, 1 November 2012 diff hist +3,170 N Using the Timing Analyzer New page: Xilinx's Timing Analyzer can be used to find fixed timing errors with your design. If you design "works perfectly in simulation, but not in hardware", and when you build a bitfile and the...
- 01:3401:34, 1 November 2012 diff hist +33 Main Page →Convey HC-1 Tutorials
29 October 2012
- 04:0604:06, 29 October 2012 diff hist +2 Analyze the Simpleton Basic App No edit summary
- 04:0504:05, 29 October 2012 diff hist +3,129 N Using the Write-Complete Interface New page: There's an optional (advanced) interface for indicating when a write completes (along with the ability to send 17 bits of write-complete control data with the write request in order to ID ... current
- 03:5803:58, 29 October 2012 diff hist +41 Main Page →Articles
- 03:5703:57, 29 October 2012 diff hist +157 m Running Different Bitfiles on each AE No edit summary current
22 October 2012
- 04:5104:51, 22 October 2012 diff hist −285 Running the Vector Adder Example Application →Interactive Mode for ModelSim Simulation
- 00:3100:31, 22 October 2012 diff hist +101 Main Page →Helpful Guides
25 September 2012
- 23:5023:50, 25 September 2012 diff hist +118 Running Different Bitfiles on each AE No edit summary
- 23:4823:48, 25 September 2012 diff hist 0 N File:Mkaetgz.txt No edit summary current
- 23:3923:39, 25 September 2012 diff hist +50 Running the Vector Adder Example Application →Interactive Mode for ModelSim Simulation
- 23:3823:38, 25 September 2012 diff hist +86 Running the Vector Adder Example Application →Interactive Mode for ModelSim Simulation
- 23:3423:34, 25 September 2012 diff hist +156 Running Different Bitfiles on each AE No edit summary
- 23:3223:32, 25 September 2012 diff hist +34 Main Page →Convey HC-1 Tutorials
- 23:2823:28, 25 September 2012 diff hist +459 Using ISE's Core Generator to build FIFOs and other IP cores No edit summary
- 23:2323:23, 25 September 2012 diff hist +1 Convey environment setup No edit summary
- 23:2223:22, 25 September 2012 diff hist +94 N Using ISE's Core Generator to build FIFOs and other IP cores New page: # Open Xilinx's ISE from the terminal (make sure your environmental variables are set): ise &
- 23:2123:21, 25 September 2012 diff hist +785 N Running Different Bitfiles on each AE New page: == Running different bitfiles on each AE == Source: http://www.ccm.ece.vt.edu/twiki/bin/view/Main/Convey The runtime environment supports multiple bitfiles making up a single personality ...
- 22:5922:59, 25 September 2012 diff hist +44 Main Page →Convey HC-1 Tutorials