Main Page
Articles
Convey HC-1 Tutorials
- Connecting to convey-1.ece.iastate.edu
- Setting Up Environment Variables on Convey's HC-1
- Convey PDK Tutorial
- Using the Memory Controller Interface
- Running the Vector Adder Example Application
- Analyze the Simpleton Basic App
- Create a Custom Bitfile
- Using a Custom Bitfile in C Code
- Adding VHDL Files to a Project
- The Verilog Hardware Interface for CAE
- Using ISE's Core Generator to build FIFOs and other IP cores
- Projects with Multiple Bitfiles
- Using the Write-Complete Interface
- Using the Timing Analyzer
- Using SPAT
- Using GPROF
- Example of Loop Unrolling using FPGA
- Speeding up Sobel Algorithm
- Frequently Asked Questions
Reference Manuals
Convey
- Convey PDK Reference Manual (.pdf) (updated to V5.2; April 2012)
- Convey Programmers Guide (.pdf) (updated to V1.8; November 2010)
- Convey Reference Manual (.pdf)
- Convey SPAT (Simulator Performance Analysis Tool) Guide
- Convey PDK (.pdf)
- Convey Overview (.pdf)
The newet version of these documents are available at Convey's Support Site
CUDA
Links
- www.asic-world.com - Great Tutorials for those Learning HDLs
- MemoCODE 2012
Other Articles
Helpful Guides
- Modelsim and ISE
- The Verilog Golden Reference
- "The Shock and Awe" VHDL Tutorial
- Verilog vs. VHDL
- VHDL Simple Code Examples
- VHDL Primer
- Using VHDL components in Verilog
- Modelsim Users Guide
- Useful Modelsim Commands
- Installing CUDA on Ubuntu
- General Purpose Computation on GPUs (GPGPU)
- Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [1]
- Guide to Remote Connecting