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Articles

Convey HC-1 Tutorials

• Connecting to convey-1.ece.iastate.edu
• Setting Up Environment Variables on Convey's HC-1
• Running the Vector Adder Example Application
• Analyze the Simpleton Basic App
• Create a Custom Bitfile
• Using a Custom Bitfile in C Code
• Adding VHDL Files to a Project
• The Verilog Hardware Interface for CAE
• Using ISE's Core Generator to build FIFOs and other IP cores
• Projects with Multiple Bitfiles
• Using the Write-Complete Interface
• Using the Timing Analyzer

• Using SPAT
• Using GPROF
• Example of Loop Unrolling using FPGA
• Speeding up Sobel Algorithm

Reference Manuals

Convey

• Convey PDK Reference Manual (.pdf) (updated to V5.2; April 2012)
• Convey Programmers Guide (.pdf) (updated to V1.8; November 2010)
• Convey Reference Manual (.pdf)
• Convey SPAT (Simulator Performance Analysis Tool) Guide
• Convey PDK (.pdf)
• Convey Overview (.pdf)

The newet version of these documents are available at Convey's Support Site

CUDA

• CUDA_C_Programming_Guide (.pdf)
• CUDA_C_Best_Practices_Guide(.pdf)
• CUDA_Memory (.pdf)

Links

• www.asic-world.com - Great Tutorials for those Learning HDLs
• MemoCODE 2012
  • MemoCODE Contest.pdf
  • Reference Implementation
  • Human Reference Genome (human_g1k_v37.fasta.gz)
  • Example Reads (ERR050082.filt.fastq.gz)
  • Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)

• CprE 584 2010 Wiki Main Page
• CprE 583 Website
• CprE 584 Website

Other Articles

• Assignments
• A quick start on CUDA

Helpful Guides

• Modelsim and ISE
• The Verilog Golden Reference
• "The Shock and Awe" VHDL Tutorial
• VHDL Simple Code Examples
• VHDL Primer
• Using VHDL components in Verilog

Readings for Memocode 2012

• A survey on algorithms for sequencing
• Burrows-Wheeler indexing

Spring 2012 Teams

• Team Gryffindor
• Team Slytherin
• Team 142857