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* [[Using ISE's Core Generator to build FIFOs and other IP cores]] | * [[Using ISE's Core Generator to build FIFOs and other IP cores]] | ||
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]] | * [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]] | ||
* [[Using the Write-Complete Interface]] | |||
* [[Using SPAT]] | * [[Using SPAT]] | ||
* [[Using GPROF]] | * [[Using GPROF]] | ||
Revision as of 03:58, 29 October 2012
Articles
Convey HC-1 Tutorials
- Connecting to convey-1.ece.iastate.edu
- Setting Up Environment Variables on Convey's HC-1
- Running the Vector Adder Example Application
- Analyze the Simpleton Basic App
- Create a Custom Bitfile
- Using a Custom Bitfile in C Code
- Adding VHDL Files to a Project
- The Verilog Hardware Interface for CAE
- Using ISE's Core Generator to build FIFOs and other IP cores
- Projects with Multiple Bitfiles
- Using the Write-Complete Interface
- Using SPAT
- Using GPROF
- Example of Loop Unrolling using FPGA
- Speeding up Sobel Algorithm
Reference Manuals
Convey
- Convey PDK Reference Manual (.pdf) (updated to V5.2; April 2012)
- Convey Programmers Guide (.pdf) (updated to V1.8; November 2010)
- Convey Reference Manual (.pdf)
- Convey SPAT (Simulator Performance Analysis Tool) Guide
- Convey PDK (.pdf)
- Convey Overview (.pdf)
- Convey Overview (.pdf)
The newet version of these documents are available at Convey's Support Site
CUDA
Links
Other Articles
Helpful Guides
- The Verilog Golden Reference
- "The Shock and Awe" VHDL Tutorial
- VHDL Simple Code Examples
- VHDL Primer
- Using VHDL components in Verilog