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== Articles == | == Articles == | ||
=== HC-1 Tutorials === | === Convey HC-1 Tutorials === | ||
* [[Connecting to convey-1.ece.iastate.edu]] | * [[Connecting to convey-1.ece.iastate.edu]] | ||
* [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]] | * [[Convey environment setup|Setting Up Environment Variables on Convey's HC-1]] | ||
| Line 17: | Line 12: | ||
* [[Convey vector example | Example of Loop Unrolling using FPGA]] | * [[Convey vector example | Example of Loop Unrolling using FPGA]] | ||
* [[Sobel Algorithm | Speeding up Sobel Algorithm]] | * [[Sobel Algorithm | Speeding up Sobel Algorithm]] | ||
== Reference Manuals == | == Reference Manuals == | ||
| Line 50: | Line 41: | ||
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website] | * [http://class.ee.iastate.edu/cpre583/ CprE 583 Website] | ||
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website] | * [http://class.ece.iastate.edu/cpre584/ CprE 584 Website] | ||
=== Other Articles === | |||
* [[Assignment|Assignments]] | |||
* [[A quick start on CUDA]] | |||
== Helpful Guides == | == Helpful Guides == | ||
| Line 56: | Line 51: | ||
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer] | * [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer] | ||
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog] | * [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog] | ||
==Readings for Memocode 2012== | |||
== Readings for Memocode 2012 == | |||
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]] | *[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]] | ||
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]] | *[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]] | ||
== Spring 2012 Teams == | |||
* [[Team Gryffindor]] | |||
* [[Team Slytherin]] | |||
* [[Team 142857]] | |||
Revision as of 03:19, 18 September 2012
Articles
Convey HC-1 Tutorials
- Connecting to convey-1.ece.iastate.edu
- Setting Up Environment Variables on Convey's HC-1
- Running the Vector Adder Example Application
- Create a Custom Bitfile
- Using a Custom Bitfile in C Code
- Adding VHDL Files to a Project
- The Verilog Hardware Interface for CAE
- Using SPAT
- Using GPROF
- Example of Loop Unrolling using FPGA
- Speeding up Sobel Algorithm
Reference Manuals
Convey
- Convey PDK Reference Manual (.pdf) (updated to V5.2; April 2012)
- Convey Programmers Guide (.pdf) (updated to V1.8; November 2010)
- Convey Reference Manual (.pdf)
- Convey SPAT (Simulator Performance Analysis Tool) Guide
- Convey PDK (.pdf)
- Convey Overview (.pdf)
- Convey Overview (.pdf)
The newet version of these documents are available at Convey's Support Site
CUDA
Links
Other Articles
Helpful Guides
- "The Shock and Awe" VHDL Tutorial
- VHDL Simple Code Examples
- VHDL Primer
- Using VHDL components in Verilog