Tutorials: Difference between revisions
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*[[Cadence SoC RTL Compiler]] - Synthesize verilog to schematic | *[[Cadence SoC RTL Compiler]] - Synthesize verilog to schematic | ||
*[[Cadence SoC Place and Route]] - Generate layout for synthesized netlist | *[[Cadence SoC Place and Route]] - Generate layout for synthesized netlist | ||
==Cadence 6.1== | |||
During the summer of 2010 ISU will be migrating all student labs to Cadence 6.1. Tutorials pertaining to Cadence 6.1 are being created and will appear here during late Spring 2010 semester. | |||
==Misc== | ==Misc== | ||
Revision as of 14:11, 15 January 2010
Analog/Mixed-Signal Software Tutorials
- icfb setup - How to set up and run Cadence Virtuoso front-to-back IC design toolset for the first time
- Neocircuit setup - Setup for Neocircuit, a sophisticated circuit-optimization tool
Analog Simulation Techniques
- Temperature sensor test - Test benches / equations for temp sensor performance measurements
- Data converter test - Methods for testing the performance of ADCs and DACs
Digital Tutorials
- Cadence SoC RTL Compiler - Synthesize verilog to schematic
- Cadence SoC Place and Route - Generate layout for synthesized netlist
Cadence 6.1
During the summer of 2010 ISU will be migrating all student labs to Cadence 6.1. Tutorials pertaining to Cadence 6.1 are being created and will appear here during late Spring 2010 semester.