Xilinx EDK
General
Documentation
Setup and Configuration
Adding a Peripheral
First connect to a machine with the right software. If it is xilinx.ece.iastate.edu or another Linux machine use NX client or SSH.
ssh -Y xilinx.ece.iastate.edu
Then source the correct files.
source /usr/local/bin/Xilinx_src
Next start up coregen to generate a FIFO.
coregen &
Start a new project.
Start up the fifo_generator wizard by clicking on the link on the left hand side.
Once the core is created, go to Xilinx EDK and open the [1].
xps &
Go to the create and import peripheral wizard to add a new peripheral.
The three registers allow for an input data register, output data register and a status register. These can be configured to support your architecture design.
When the peripheral is created, an ISE project file is automatically created as well.
<base project>/pcores/fifo_peripheral_v1_00_a/devl/projectnav/fifo_peripheral.ise
Open this project in ISE
ise &
Edit the user_logic.vhd file to include the peripheral generated from coregen. Add it as a component, make two instances of the FIFO and then connect the two together. Finally wire the connected FIFO to the registers that were created in EDK. This is also where a more complicated hardware design would be added.
ISE does not know where to find the coregen created components so they must be imported. Add the .xco file from the directory where you created the coregen component to the ISE project.
Finally, in ISE syntax checking and simulations can be performed to check that the code works correctly.
When the project works in ISE go back to EDK and re-run the Create and Import Peripheral Wizard. Make sure to select the same filename as the first time and the same revision number.
After these steps, the peripheral will be re-imported and EDK will know about the coregen files that were created earlier. If any errors occurred, go back to ISE and fix the syntax on the VHDL first then come back and try to re-import.
In EDK add the IP for the peripheral to the project by right clicking on it in the left hand window and selecting add IP.
The peripheral should appear in the System Assembly View.
Connect to the peripheral to the bus by either clicking the open circle in the left pane or using the drop down menu to select the PLB.
Next, generate an address range for the new peripheral by clicking on the Generate Addresses button in the top left corner.
Edit the C code to utilize the new peripheral and also to mediate between the serial port and the PLB bus.
Generate simulation files for the project and simulate it in Modelsim. Check to see that the peripheral is working as expected. It should be noted that the previous picture has references to the UART module. These should be commented out prior to simulation. The relatively little amount of time that can be simulated will not be enough to show proper UART functioning.
Generate a bitstream. This process takes a while (~1 hour) but subsequent bitstream generations move much quicker.
Download the bitstream to the board. Make sure it is connected to the computer and that a serial cable is also connected. The Xil_print statements in the C code use the RS232 port to communicate.
Start up minicom on the computer that the serial cable from the board is connected to. When you type in minicom it will be sent to the board, through the FIFOs and back out to minicom. Depending on how you implemented the VHDL, there may be a delay for the characters to echo back.
sudo minicom
