User contributions for Ogamal

4 September 2015

• 03:5003:50, 4 September 2015 diff hist −1‎ Convey PDK Tutorial ‎No edit summary current
• 03:5003:50, 4 September 2015 diff hist +6‎ Convey PDK Tutorial ‎No edit summary
• 03:4903:49, 4 September 2015 diff hist +1‎ Convey PDK Tutorial ‎No edit summary
• 03:4903:49, 4 September 2015 diff hist +91‎ Convey PDK Tutorial ‎No edit summary
• 03:4803:48, 4 September 2015 diff hist +18‎ Convey PDK Tutorial ‎No edit summary
• 03:4803:48, 4 September 2015 diff hist −1‎ Convey PDK Tutorial ‎No edit summary
• 03:4703:47, 4 September 2015 diff hist +60‎ Convey PDK Tutorial ‎No edit summary

25 April 2013

• 02:0902:09, 25 April 2013 diff hist 0‎ Frequently Asked Questions ‎ →‎General FAQ current
• 02:0802:08, 25 April 2013 diff hist +136‎ Frequently Asked Questions ‎ →‎How to start my own custom personality project?

4 April 2013

• 04:0304:03, 4 April 2013 diff hist +80‎ Frequently Asked Questions ‎ →‎How to read/write the memory in the emulator?

26 February 2013

• 23:4023:40, 26 February 2013 diff hist −1‎ Frequently Asked Questions ‎No edit summary
• 23:3823:38, 26 February 2013 diff hist +503‎ Frequently Asked Questions ‎ →‎Simulator Related

14 February 2013

• 00:3000:30, 14 February 2013 diff hist +1‎ Frequently Asked Questions ‎ →‎Why ModelSim ends the simulation before my design finish?
• 00:3000:30, 14 February 2013 diff hist +271‎ Frequently Asked Questions ‎ →‎Simulator Related

13 February 2013

• 08:4608:46, 13 February 2013 diff hist 0‎ Adding VHDL Files to a Project ‎ →‎Instantiation in Verilog
• 08:4608:46, 13 February 2013 diff hist +257‎ Adding VHDL Files to a Project ‎ →‎Instantiation in Verilog

12 February 2013

• 23:2723:27, 12 February 2013 diff hist 0‎ File:Cyc05 week4 presentation.pdf ‎ uploaded a new version of "Image:Cyc05 week4 presentation.pdf" current
• 23:1923:19, 12 February 2013 diff hist +81‎ Team Cyc05 ‎ →‎Weekly Presentations
• 23:1923:19, 12 February 2013 diff hist 0‎ N File:Cyc05 week4 presentation.pdf ‎No edit summary
• 23:1823:18, 12 February 2013 diff hist 0‎ File:Cyc05 week3 presentation.pdf ‎ uploaded a new version of "Image:Cyc05 week3 presentation.pdf" current
• 23:1823:18, 12 February 2013 diff hist 0‎ File:Cyc05 week3 presentation.pdf ‎ uploaded a new version of "Image:Cyc05 week3 presentation.pdf"
• 05:0105:01, 12 February 2013 diff hist +52‎ Using ISE's Core Generator to build FIFOs and other IP cores ‎ →‎How-to
• 00:1600:16, 12 February 2013 diff hist +7‎ Team Cyc05 ‎ →‎Osama
• 00:1500:15, 12 February 2013 diff hist +91‎ Team Cyc05 ‎ →‎Osama
• 00:1400:14, 12 February 2013 diff hist +183‎ N File:Vhd2v isnt.txt ‎ Simple script to read a VHDL module and generate code to instantiate it in Verilog NOTE: change script name to "vhd2v_inst.py" first then run as: "python vhd2v_inst.py <filename.vhd>" current
• 00:1200:12, 12 February 2013 diff hist +1‎ Main Page ‎No edit summary

11 February 2013

• 22:0522:05, 11 February 2013 diff hist +226‎ Team Cyc05 ‎ →‎Osama
• 22:0522:05, 11 February 2013 diff hist 0‎ File:Convey mc ports.txt ‎ uploaded a new version of "Image:Convey mc ports.txt" current
• 22:0322:03, 11 February 2013 diff hist 0‎ File:Convey mc ports.txt ‎ uploaded a new version of "Image:Convey mc ports.txt"
• 21:5821:58, 11 February 2013 diff hist +149‎ N File:Convey mc ports.txt ‎ Rename the file back to "convey_mc_ports.py" and run it using the command "python convey_mc_ports.py". NOTE: doesn't run on python version before 2.6
• 21:5021:50, 11 February 2013 diff hist +48‎ N File:Convey mc ports vhdl.txt ‎ Convey memory controller interface ports in vhdl current

8 February 2013

• 01:1401:14, 8 February 2013 diff hist +6‎ Main Page ‎No edit summary
• 01:1401:14, 8 February 2013 diff hist +2‎ Frequently Asked Questions ‎No edit summary
• 01:1401:14, 8 February 2013 diff hist +10‎ Frequently Asked Questions ‎No edit summary
• 01:1301:13, 8 February 2013 diff hist +1‎ Frequently Asked Questions ‎No edit summary
• 01:1201:12, 8 February 2013 diff hist +331‎ Frequently Asked Questions ‎No edit summary
• 00:3000:30, 8 February 2013 diff hist −1‎ Frequently Asked Questions ‎No edit summary
• 00:3000:30, 8 February 2013 diff hist +511‎ Frequently Asked Questions ‎No edit summary

6 February 2013

• 00:1100:11, 6 February 2013 diff hist −1‎ Using the Memory Controller Interface ‎ →‎Memory Controller Interface functionality current
• 00:0500:05, 6 February 2013 diff hist 0‎ N File:Cyc05 Week 3.pdf ‎No edit summary current
• 00:0000:00, 6 February 2013 diff hist 0‎ Using the Memory Controller Interface ‎ →‎Reading from Memory
• 00:0000:00, 6 February 2013 diff hist −4‎ Using the Memory Controller Interface ‎ →‎Reading from Memory

5 February 2013

• 23:5923:59, 5 February 2013 diff hist +51‎ Using the Memory Controller Interface ‎ →‎Reading from Memory
• 23:5723:57, 5 February 2013 diff hist −1‎ Using the Memory Controller Interface ‎ →‎Writing to Memory
• 23:4923:49, 5 February 2013 diff hist +113‎ Using the Memory Controller Interface ‎No edit summary
• 23:4723:47, 5 February 2013 diff hist +17‎ Using the Memory Controller Interface ‎ →‎Memory Controller Interface functionality
• 23:4523:45, 5 February 2013 diff hist +102‎ Using the Memory Controller Interface ‎ →‎Reading from Memory
• 23:3723:37, 5 February 2013 diff hist +530‎ Using the Memory Controller Interface ‎No edit summary
• 23:2823:28, 5 February 2013 diff hist +144‎ Team Cyc05 ‎ →‎Wiki Contributions
• 23:2423:24, 5 February 2013 diff hist +415‎ Using the Memory Controller Interface ‎ →‎Reading from Memory