Using ISE's Core Generator to build FIFOs and other IP cores

1. Open Xilinx's ISE from the terminal (make sure your environmental variables are set):

ise &

1. Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
2. Open the Core Generator (Tools -> Core Generator...)
3. Create a new Core Generator project.
   1. Part
      1. Family: Virtex5
      2. Device: xc5vlx330
      3. Package: ff1760
      4. Speed: -2
   2. Generation
      1. Simulation Model: Structural
4. Generate you IP Cores!
5. Copy the .ngc, .v, and .xco to the coregen folder in your PDK project