Using ISE's Core Generator to build FIFOs and other IP cores
- Open Xilinx's ISE from the terminal (make sure your environmental variables are set):
ise &
- Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
- Open the Core Generator (Tools -> Core Generator...)
- Create a new Core Generator project.
- Part
- Family: Virtex5
- Device: xc5vlx330
- Package: ff1760
- Speed: -2
- Generation
- Simulation Model: Structural
- Part
- Generate you IP Cores!
- Copy the .ngc, .v, and .xco to the coregen folder in your PDK project