Running the Vector Adder Example Application

Section 10.5 of PDK Reference Manual explains how to run the sample software application. It has been reproduced below in brief.

Compiling the Project

The rev version installed on the Convey machine is from 2011-11-22; to copy the sample app's source code run:

cd ~
mkdir pdk_sample
cp -r /opt/convey/pdk/latest/hc-1/examples/* pdk_sample

To make the sample project, first make sure you have setup your environment variables, then run:

cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/
make

This compiles both an emulator (CaeSimPers) and a C program that makes a coprocessor call to use the vector adder (UserApp.exe).

Run the Project

Projects typically contain the following three executables:

1. A software simulation of the FPGA design
2. A hardware simulation (ModelSim) of the FPGA design
3. The actual implementation (C code, Verilog code). The bitfiles are compiled, nicknamed, and added to a known file location.

Actual Implementation

To run the software version of the app that makes a call to the coprocessor, use the command:

cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/
./UserApp.exe

You should see the program run and output the following:

You can also set the CNY_CALL_STATS environment variable; this variable gives back the number of times the coprocessor was called. I.E. for this application, the coprocessor is called once. Output from the terminal is reproduced in the following file:

Console Output

Software Simulation

Set the environmental variables to use the software simulation of the coprocessor:

# Use the Coprocessor Simulator
export CNY_SIM_THREAD=libcpSimLib2.so
# Point to the emulator
export CNY_CAE_EMULATOR=~/pdk_sample/cae_pers_vadd/CaeSimPers/CaeSimPers

After setting the environmental variables, rerun the app:

cd ~/pdk_sample/SampleAppVadd/
./UserApp.exe

The program will pause at the following screen for a 10-20 seconds...

...and then finish running the program.