Main Page

Teams

• Team Gryffindor
• Team Slytherin
• Team 142857

Articles

• Assignments
• Connecting to convey-1.ece.iastate.edu
• Setting Up Environment Variables on Convey's HC-1
• Running the Vector Adder Example Application
• Example of Loop Unrolling using FPGA
• Create a Custom Bitfile
• Using a Custom Bitfile in C Code
• Speeding up Sobel Algorithm
• Using SPAT
• Using GPROF
• Adding VHDL Files to a Project
• The Verilog Hardware Interface for CAE
• A quick start on CUDA

Reference Manuals

• Convey PDK Reference Manual (.pdf) (updated to V5; November 2011)
• Convey Programmers Guide (.pdf) (updated to V1.8; November 2010)
• Convey Reference Manual (.pdf)
• Convey SPAT (Simulator Performance Analysis Tool) Guide
• Convey PDK (.pdf)
• Convey Overview (.pdf)
• Convey Overview (.pdf)
• CUDA_C_Programming_Guide (.pdf)
• CUDA_C_Best_Practices_Guide(.pdf)

The newest version of these documents are available at Convey's Support Site

Links

• MemoCODE 2012
  • MemoCODE Contest.pdf
  • Reference Implementation
  • Human Reference Genome (human_g1k_v37.fasta.gz)
  • Example Reads (ERR050082.filt.fastq.gz)

• 2010 Main Page
• CprE 583 Website
• CprE 584 Website

Helpful Guides

• "The Shock and Awe" VHDL Tutorial
• VHDL Simple Code Examples
• Using VHDL components in Verilog