Team Cyc05

Team Cyc05

Cyc05 Team Logo
Team Members Osama G. Attia (ogamal) Tyler Johnson (tyler07) PengQing Xie (carterp)

Team Members

• Osama G. Attia
• Tyler Johnson
• PengQing Xie

Weekly Presentations

• Week 1 - Presentation Slides Week 1
• Week 2 - Presentation Slides Week 2
• Week 3 - Presentation Slides Week 3
• Week 4 - Presentation Slides Week 4

Wiki Contributions

Tyler

• Week 1
  • Useful Modelsim Commands
  • Modelsim Users Guide
• Week2
  • Guide to Remote Connecting
• Week3
  • Adding VHDL Files to a Project Additions and alterations
  • Hosted the scripts for Kevinss tutorial and provided a link for it
  • Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
  • Modified Tutorial: Creating a Custom Bitfile, some details were unclear and/or left out about using your newly built bitfile
• Week 4
  • Added a topic to the FAQ page regarding how you can use the /tmp/ directory in order to speed up certain activities such as building a bitfile or simulation. Added this script to help with migration.
• Week 5
  • Added instructions for simulating an IP core made with ISE corgen. This is mostly for when you would like to use your own testbench, I believe Coney's testbench will work without these steps
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Osama

• Week 1: Creating Team Cyc05 page.
• Week 2:
  • Updating Connecting to convey-1.ece.iastate.edu with usage policy
  • Adding Frequently Asked Questions page
• Week 3:
  • Updating the Frequently Asked Questions page
  • Adding and maintaining the Using the Memory Controller Interface page
• Week 4:
  • Python script to generate instantiation code of VHDL module in Verilog
  • Python script to generate the MC interface signals in VHDL
  • MC interface signals in VHDL
  • Adding more stuff to the Frequently Asked Questions page

PengQing

• Week 1:
  • Installing CUDA on Ubuntu
  • General Purpose Computation on GPUs (GPGPU)
• Week 2:
  • Verilog self-study online course
• Week 3:
  • Verilog vs. VHDL
• Week 4:
  • git tutorial