Team Cyc05: Difference between revisions

Revision as of 22:05, 11 February 2013

Team Cyc05

Cyc05 Team Logo

Week 1
- Useful Modelsim Commands
- Modelsim Users Guide
Week2
- Guide to Remote Connecting
Week3
- Adding VHDL Files to a Project Additions and alterations
- Hosted the scripts for Kevinss tutorial and provided a link for it
- Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
- Modified Tutorial: Creating a Custom Bitfile, some details were unclear and/or left out about using your newly built bitfile

Week 1: Creating Team Cyc05 page.
Week 2:
- Updating Connecting to convey-1.ece.iastate.edu with usage policy
- Adding Frequently Asked Questions page
Week 3:
- Updating the Frequently Asked Questions page
- Adding and maintaining the Using the Memory Controller Interface page
Week 4:
- Adding more stuff to the Frequently Asked Questions page
- Python script to generate the MC interface signals in VHDL
- MC interface signals in VHDL

@@ Line 45: / Line 45: @@
 *Week 1: Creating Team Cyc05 page.
 *Week 2:
-**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy.
+**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy
-**Adding [[Frequently Asked Questions]] page.
+**Adding [[Frequently Asked Questions]] page
 * Week 3:
-**Updating the [[Frequently Asked Questions]] page.
+**Updating the [[Frequently Asked Questions]] page
-**Adding and maintaining the [[Using the Memory Controller Interface]] page.
+**Adding and maintaining the [[Using the Memory Controller Interface]] page
+* Week 4:
+**Adding more stuff to the [[Frequently Asked Questions]] page
+**[[Media:Convey_mc_ports.txt|Python script]] to generate the MC interface signals in VHDL
+**[[Media:convey_mc_ports_vhdl.txt|MC interface signals]] in VHDL
 === PengQing ===