Team Cyc05: Difference between revisions
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**[http://vol.verilog.com/VOL/main.htm Verilog self-study online course] | **[http://vol.verilog.com/VOL/main.htm Verilog self-study online course] | ||
*Week 3: | *Week 3: | ||
**[http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL] | |||
Revision as of 23:13, 6 February 2013
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| Cyc05 Team Logo | ||||
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Team Members
- Osama G. Attia
- Tyler Johnson
- PengQing Xie
Weekly Presentations
- Week 1 - Presentation Slides Week 1
- Week 2 - Presentation Slides Week 2
- Week 3 - Presentation Slides Week 3
Wiki Contributions
Tyler
- Week 1
- Week2
- Week3
- Adding VHDL Files to a Project Additions and alterations
- Hosted the scripts for Kevinss tutorial and provided a link for it
- Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
- Modified Tutorial: Creating a Custom Bitfile, some details were unclear and/or left out about using your newly built bitfile
Osama
- Week 1: Creating Team Cyc05 page.
- Week 2:
- Updating Connecting to convey-1.ece.iastate.edu with usage policy.
- Adding Frequently Asked Questions page.
- Week 3:
- Updating the Frequently Asked Questions page.
- Adding and maintaining the Using the Memory Controller Interface page.