Using ISE's Core Generator to build FIFOs and other IP cores

Why Use Dedicated Logic

If you don't use it, you lose it! Don't let the dedicated logic (BRAMs, DSP cores) go unused... you'll hurt their feelings.

Dedicated logic improves compile times and reduces the amount of Slice Logic used. It's also FAST, and can help reduce the chance of timing errors.

How-to

1. Open Xilinx's ISE from the terminal (make sure your environmental variables are set):

ise &

1. Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
2. Open the Core Generator (Tools -> Core Generator...)
3. Create a new Core Generator project.
   1. Part
      1. Family: Virtex5
      2. Device: xc5vlx330
      3. Package: ff1760
      4. Speed: -2
   2. Generation
      1. Simulation Model: Structural
4. Generate you IP Cores!
5. Copy the .ngc, .v, and .xco to the coregen folder in your PDK project

Common IP Cores

Most IP cores can be implemented using either BRAM (Block RAM), DSP cores, or Slice logic. To give you an idea about the number of components available, there are:

• 288 36-Kilobit BRAMs available
  • BRAMs are dual port, allowing multiple small FIFOs per BRAM
• 28x15 DSP slices
• 51,840 Slices (each slice contains 4 LUTS & 4 Flip-flops)

Here are some common components you could use:

• Memories & Storage Elements -> (use Block RAM)
  • FIFOs (any port width)
  • Dual port RAM (port widths: 2, 4, 8... up to 128 bits)
• Math Functions -> (use DSP slices)
  • Adder/Subtracts (up to 48 bit)
  • Multipliers (up to 64 bit, 128 bit output)
  • Dividers (up to 32 bit)