Running the Vector Adder Example Application: Difference between revisions
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You can find the custom personality under testbench->cae_fpga->ae_top->core->cae_pers. Once you have a wave format that you want to automatically load, you can instead add a line like this: | You can find the custom personality under testbench->cae_fpga->ae_top->core->cae_pers. Once you have a wave format that you want to automatically load, you can instead add a line like this: | ||
USER_SIM_OPTIONS = -i -do sample_wave.do | USER_SIM_OPTIONS = -i -do "sample_wave.do" | ||
Where the file name sample_wave.do would contain something like this: | Where the file name sample_wave.do would contain something like this: | ||
Revision as of 21:27, 18 September 2012
Section 10.5 of the Convey PDK Reference Manual (.pdf) explains how to run the sample software application. It has been reproduced below in brief.
Compiling the Project
The rev version installed on the Convey machine is from 2012-03-19; to copy the sample app's source code run:
cd ~ mkdir pdk_sample cp -r /opt/convey/pdk/latest/hc-1/examples/* pdk_sample
To make the sample project, first make sure you have setup your environment variables, then run:
cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/ make
This compiles both an emulator (CaeSimPers) and a C program that makes a coprocessor call to use the vector adder (UserApp.exe).
Run the Project
There are three ways to run your project:
- A software simulation of the FPGA design
- A hardware simulation (ModelSim) of the FPGA design
- The actual implementation (C code, Verilog code). The bitfile was previously compiled, nicknamed, and added to a known file location (/opt/convey/personalties/...).
There are some scripts that can be used to run the various projects.
The runcp (i.e. run coprocessor) script located in the SampleAppVadd can be used to run the application in HW which sets the appropriate environment variables and runs the UserApp.exe:
./runcp
The run script located in the SampleAppVadd can be used to run the application using the software simulation of the FPGA design.
./run
Using the "-vsim" option, either script can be used to run the application using the hardware simulation (ModelSim). The "-vsim" option sets the environment variable CNY_CAE_EMULATOR to ./run_simulation:
./runcp -vsim
or
./run -vsim
To summarize the important environment variables:
| Environment Variables | Software | ModelSim | Hardware |
| CNY_SIM_THREAD | libcpSimLib2.so | libcpSimLib2.so | unset |
| CNY_CAE_EMULATOR | <location for CaeSimPers> | ./run_simulation | unset |
Interactive Mode for ModelSim Simulation
The sample project will default to command line mode when using the -vsim flag. Add the following line in the /sim makefile to have it start in interactive mode:
USER_SIM_OPTIONS = -i -do "run -all"
You can find the custom personality under testbench->cae_fpga->ae_top->core->cae_pers. Once you have a wave format that you want to automatically load, you can instead add a line like this:
USER_SIM_OPTIONS = -i -do "sample_wave.do"
Where the file name sample_wave.do would contain something like this:
do my_wave_format.do run 21 us
Where my_wave_formate.do is the wave format you created in Modelsim for formatting which signals you want to monitor.