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* TODO [[Using SPAT]] | * TODO [[Using SPAT]] | ||
* [[Adding VHDL Files to a Project]] | * [[Adding VHDL Files to a Project]] | ||
* | * [[The Verilog Hardware Interface for CAE]] | ||
== Reference Manuals == | == Reference Manuals == | ||
Revision as of 20:46, 25 February 2012
Teams
Articles
- Assignments
- Connecting to convey-1.ece.iastate.edu
- Setting Up Environment Variables on Convey's HC-1
- Running the Vector Adder Example Application
- Example of Loop Unrolling using FPGA
- Create a Custom Bitfile
- Using a Custom Bitfile in C Code
- Needs work Speeding up Sobel Algorithm
- TODO Using SPAT
- Adding VHDL Files to a Project
- The Verilog Hardware Interface for CAE
Reference Manuals
- Convey PDK Reference Manual (.pdf) (updated to V5; November 2011)
- Convey Programmers Guide (.pdf) (updated to V1.8; November 2010)
- Convey Reference Manual (.pdf)
- Convey SPAT (Simulator Performance Analysis Tool) Guide
- Convey PDK (.pdf)
- Convey Overview (.pdf)
The newest version of these documents are available at Convey's Support Site