Tutorial: Creating a Custom Bitfile: Difference between revisions
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== References == | == References == | ||
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.4.6, 9.4.7, 10 | * [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] - Sections 9.4.6, 9.4.7, 10 | ||
Revision as of 20:55, 15 February 2012
This page covers the creation and installation of a custom personality/bitfile (a modification of the vector adder sample project).
Building a Bitfile
Copy rev 2011_11_22 of the example project and set your environment variables if you have not done so already. You can make a small modification to the verilog code if you wish.
cd ~/pdk_sample/cae_vadd/phys make
The bitfile will take a long time to create (while the Reference Manual states 2 to 4 hours; mine took 18 hours to finish). Be patient.
Packaging the Bitfile
cd ~/pdk_sample/cae_vadd/phys make release
This will create a new directory (~/pdk_sample/cae_vadd.release/). The important file that is created is named cae_fpga.tgz.
Installing the Bitfile
Follow the instructions from section 9.4.7 to install the packaged bitfile.
- Rename ~/pdk_sample/cae_vadd.released/#DATE#/cae_fpga.tgz to ae_fpga.tgz
- Determine what your bitfile's signature should be
- Copy the ae_fpga.tgz file to /opt/convey/personalities/#signature#
Any ideas? We need higher privilledges add files to the /opt/convey/personalities/ folder.
Finally, flush the MP cache:
/opt/convey/sbin/mpcache –f
See Also
References
- Convey PDK Reference Manual (.pdf) - Sections 9.4.6, 9.4.7, 10