Team Cyc05: Difference between revisions
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*Week 1: Creating Team Cyc05 page. | *Week 1: Creating Team Cyc05 page. | ||
*Week 2: | *Week 2: | ||
**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy | **Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy | ||
**Adding [[Frequently Asked Questions]] page | **Adding [[Frequently Asked Questions]] page | ||
* Week 3: | * Week 3: | ||
**Updating the [[Frequently Asked Questions]] page | **Updating the [[Frequently Asked Questions]] page | ||
**Adding and maintaining the [[Using the Memory Controller Interface]] page. | **Adding and maintaining the [[Using the Memory Controller Interface]] page | ||
* Week 4: | |||
**Adding more stuff to the [[Frequently Asked Questions]] page | |||
**[[Media:Convey_mc_ports.txt|Python script]] to generate the MC interface signals in VHDL | |||
**[[Media:convey_mc_ports_vhdl.txt|MC interface signals]] in VHDL | |||
=== PengQing === | === PengQing === |
Revision as of 22:05, 11 February 2013
Cyc05 Team Logo | ||||
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Team Members
- Osama G. Attia
- Tyler Johnson
- PengQing Xie
Weekly Presentations
- Week 1 - Presentation Slides Week 1
- Week 2 - Presentation Slides Week 2
- Week 3 - Presentation Slides Week 3
Wiki Contributions
Tyler
- Week 1
- Week2
- Week3
- Adding VHDL Files to a Project Additions and alterations
- Hosted the scripts for Kevinss tutorial and provided a link for it
- Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
- Modified Tutorial: Creating a Custom Bitfile, some details were unclear and/or left out about using your newly built bitfile
Osama
- Week 1: Creating Team Cyc05 page.
- Week 2:
- Updating Connecting to convey-1.ece.iastate.edu with usage policy
- Adding Frequently Asked Questions page
- Week 3:
- Updating the Frequently Asked Questions page
- Adding and maintaining the Using the Memory Controller Interface page
- Week 4:
- Adding more stuff to the Frequently Asked Questions page
- Python script to generate the MC interface signals in VHDL
- MC interface signals in VHDL