Team Cyc05: Difference between revisions

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*Week 2 - [[Media:Cyc05_Week_2.pdf | Presentation Slides Week 2]]
*Week 2 - [[Media:Cyc05_Week_2.pdf | Presentation Slides Week 2]]
*Week 3 - [[Media:Cyc05_week3_presentation.pdf‎ | Presentation Slides Week 3]]
*Week 3 - [[Media:Cyc05_week3_presentation.pdf‎ | Presentation Slides Week 3]]
*Week 4 - [[Media:Cyc05_week4_presentation.pdf‎ | Presentation Slides Week 4]]


== Wiki Contributions ==
== Wiki Contributions ==
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**Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
**Modified the landing page to Kevni't tutorial to have the pdf, and a link to the scripts
**Modified [[Tutorial: Creating a Custom Bitfile]], some details were unclear and/or left out about using your newly built bitfile
**Modified [[Tutorial: Creating a Custom Bitfile]], some details were unclear and/or left out about using your newly built bitfile
*Week 4
**Added a topic to the FAQ page regarding how you can use the /tmp/ directory in order to speed up certain activities such as building a bitfile or simulation. Added [[Media:UseTmpScript.sh‎ | this script]] to help with migration.
*Week 5
**Added instructions for simulating an IP core made with ISE corgen. This is mostly for when you would like to use your own testbench, I believe Coney's testbench will work without these steps
***[[Using ISE's Core Generator to build FIFOs and other IP cores]]


=== Osama ===
=== Osama ===
*Week 1: Creating Team Cyc05 page.
*Week 1: Creating Team Cyc05 page.
*Week 2:
*Week 2:
**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy.
**Updating [[Connecting to convey-1.ece.iastate.edu]] with usage policy
**Adding [[Frequently Asked Questions]] page.
**Adding [[Frequently Asked Questions]] page
* Week 3:
* Week 3:
**Updating the [[Frequently Asked Questions]] page.
**Updating the [[Frequently Asked Questions]] page
**Adding and maintaining the [[Using the Memory Controller Interface]] page.
**Adding and maintaining the [[Using the Memory Controller Interface]] page
* Week 4:
**[[Media:Vhd2v isnt.txt|Python script to generate instantiation code of VHDL module in Verilog]]
**[[Media:Convey_mc_ports.txt|Python script to generate the MC interface signals in VHDL]]
**[[Media:convey_mc_ports_vhdl.txt|MC interface signals]] in VHDL
**Adding more stuff to the [[Frequently Asked Questions]] page


=== PengQing ===
=== PengQing ===
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**[http://vol.verilog.com/VOL/main.htm Verilog self-study online course]
**[http://vol.verilog.com/VOL/main.htm Verilog self-study online course]
*Week 3:
*Week 3:
***[http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL]
**[http://www.ece.msstate.edu/~reese/EE4743/lectures/verilog_intro_2002/verilog_intro_2002.pdf Verilog vs. VHDL]
*Week 4:
**[http://www.vogella.com/articles/Git/article.html git tutorial]

Latest revision as of 04:40, 15 February 2013

Team Cyc05
Cyc05 Team Logo
Team Members
Osama G. Attia (ogamal)
Tyler Johnson (tyler07)
PengQing Xie (carterp)

Team Members

  • Osama G. Attia
  • Tyler Johnson
  • PengQing Xie

Weekly Presentations

Wiki Contributions

Tyler

Osama

PengQing