Using ISE's Core Generator to build FIFOs and other IP cores

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Why Use Dedicated Logic

If you don't use it, you lose it! Don't let the dedicated logic (BRAMs, DSP slices) go unused... you'll hurt their feelings.

Dedicated logic improves compile times and reduces the amount of Slice Logic used. It's also FAST, and can help reduce the chance of timing errors. For example, the DSP slices can operate at 550 MHz.

How-to

  1. Open Xilinx's ISE from the terminal (make sure your environmental variables are set):
ise &
  1. Create or open a project. The devices on the HC-1 and HC-2 are Virtex 5 FPGAs (xc5vlx330, -2, ff1760).
  2. Open the Core Generator (Tools -> Core Generator...)
  3. Create a new Core Generator project.
    1. Part
      1. Family: Virtex5
      2. Device: xc5vlx330
      3. Package: ff1760
      4. Speed: -2
    2. Generation
      1. Simulation Model: Structural
  4. Generate you IP Cores!
  5. Create folder named "coregen" in your PDK proejct
  6. Copy the .ngc, .v, and .xco to the coregen folder in your PDK project

Common IP Cores

Most IP cores can be implemented using either BRAM (Block RAM), DSP cores, or Slice logic. To give you an idea about the number of components available, there are:

  • 288 36-Kilobit BRAMs available
    • BRAMs are dual port, allowing multiple small FIFOs per BRAM
  • 28x15 DSP slices
  • 51,840 Slices (each slice contains 4 LUTS & 4 Flip-flops)

Here are some common components you could use:

  • Memories & Storage Elements -> (use Block RAM)
    • FIFOs (any port width)
    • Dual port RAM (port widths: 2, 4, 8... up to 128 bits)
  • Math Functions -> (use DSP slices)
    • Adder/Subtracts (up to 48 bit)
    • Multipliers (up to 64 bit, 128 bit output)
    • Dividers (up to 32 bit)

Simulating IP Cores With Modelsim (For a Custom Testbench)

So you have just used coregen to make your IP core and you would like to use it in your testbench. The steps below will show you how you can successfully simulate the IP core.

  • Add the .v or .vhd files to your Modelsim project so that when they are compilied they show up in your work
  • At the top of the module that you will be using to instantiate the new IP core, add the following:
    • Library UNISIM;
    • USE UNISIM.VCOMPONENTS.ALL;
  • Now in the Modelsim console run the following command:
    • vmap <library> <path to library>
    • For our purposes this will be:
      • VHDL - vmap unisim /remote/Xilinx/13.4/ISE/vhdl/mti_se/10.1c/lin64/unisim/
      • Verilog - vmap unisim /remote/Xilinx/13.4/ISE/verilog/mti_se/10.1c/lin64/unisim/
  • If your corgen module depends on the xilinxcorelib you will also want to map this library
    • vmap xilinxcorelib /remote/Xilinx/13.4/ISE/vhdl/mti_se/10.1c/lin64/xilinxcorelib

(These paths are subject to change, they were added on 2/14/13)