Running the Vector Adder Example Application
Section 10.5 of the Convey PDK Reference Manual (.pdf) explains how to run the sample software application. It has been reproduced below in brief.
Compiling the Project
The rev version installed on the Convey machine is from 2012-03-19; to copy the sample app's source code run:
cd ~ mkdir pdk_sample cp -r /opt/convey/pdk/latest/hc-1/examples/* pdk_sample
To make the sample project, first make sure you have setup your environment variables, then run:
cd ~/pdk_sample/cae_pers_vadd/SampleAppVadd/ make
This compiles both an emulator (CaeSimPers) and a C program that makes a coprocessor call to use the vector adder (UserApp.exe).
Run the Project
There are three ways to run your project:
- A software simulation of the FPGA design
- A hardware simulation (ModelSim) of the FPGA design
- The actual implementation (C code, Verilog code). The bitfile was previously compiled, nicknamed, and added to a known file location (/opt/convey/personalties/...).
There are some scripts that can be used to run the various projects.
The runcp (i.e. run coprocessor) script located in the SampleAppVadd can be used to run the application in HW which sets the appropriate environment variables and runs the UserApp.exe:
The run script located in the SampleAppVadd can be used to run the application using the software simulation of the FPGA design.
Using the "-vsim" option, either script can be used to run the application using the hardware simulation (ModelSim). The "-vsim" option sets the environment variable CNY_CAE_EMULATOR to ./run_simulation:
./runcp -vsim or ./run -vsim
To summarize the important environment variables:
|CNY_CAE_EMULATOR||<location for CaeSimPers>||./run_simulation||unset|
Interactive Mode for ModelSim Simulation
You can save the waveforms every time you run the hardware simulator to make debugging easier.
Add the $wlfdumpvars line to the sim/tb_user.v file:
// To trace everything (slow) $wlfdumpvars(0, testbench); // To trace cae_pers module and 5 levels below `ifdef AE0_PRESENT $wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);
Then include that file in the sim/Makefile by adding this line this line: CNY_PDK_TB_USER_VLOG += ./tb_user.v
This will create a vsim.wlf file in the sim directory. You can view the waveform using any of the following terminal commands:
vsim ../sim/vsim.wlf vsim -view ../sim/vsim.wlf
Alternatively, you may instead run the simulation in interactive mode by adding the following line to the makefile in the sim directory:
USER_SIM_OPTIONS = -gui
Then run the app (./run -vsim) to start the simulation. When the Modelsim GUI opens and the design is loaded, type “run -all” at the Modelsim command line.