Frequently Asked Questions

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General FAQ

How to start my own custom personality project?

We have two sample PDK examples. You can either use the cnyScript as described in this tutorial: Convey PDK Tutorial or use the Simpleton sample which is described in: Analyze the Simpleton Basic App.

How to add new verilog files or directories to a PDK project?

By default, the PDK looks like the project/verilog directory and compiles all .v files found there. To add other Verilog directories, use this makefile variable:
USER_VERILOG_DIRS += ../../verilog

Why is Simulation/building bit file/ (insert here) so slow?

If you are using the the cyfiles drive to do your work, these activities all seem to run much slower. The reason is that the cyfiles is a network mapped drive, so all reads/writes will have to traverse the network. To get around this, you can use the /tmp/ directory. You can copy your project to a directory, such as /tmp/.[username]/[projectfile]. The tmp directories are occasionally cleaned out, so do not leave unsaved work there. Here‎ is a script that will copy a give folder the the path of /tmp/.[username]/[name of folder]. The script will check to see if there is already a directory there with the same name, and if so it will alert the user. If not it will just copy the directory. *IMPORTANT* Ensure to make a copy of any changes back into your actual working directory, since the /tmp/ directory is routinely cleaned up.

Simulator Related

Where can I find the personality signals?

You can find your custom personality signals in the "sim" window in ModelSim under testbench > cae_fpga0 > ae_top > core > cae_pers

Why ModelSim ends the simulation before my design finish?

Convey simulations are set to end after a specific time period. To change this time, modify the following line in the file sim/sc.config in your pdk project:

set DeadMan 10000

How to keep the waves I simulated?

After adding the signals to the wave window, make sure to click anywhere in the waves window. Then, click the save button and save the current signals as "do" file. Next time you want to show the previous signals, open ModelSim using the command:

vsim &

Then, in the ModelSim command-line, type:

do sim/

Finally, click the "open" button and open the "vsim.wlf" file in the "sim" directory of your project.

How to run Modelsim GUI while simulating?

You may run the simulation in interactive mode by adding the following line to the makefile in the sim directory:


Another option is to edit the test bench (sim/tb_user.v shown below) to dump the waveforms to a file, then run the hardware simulator via command line, and finally open up the waveform file (vsim -v ./sim/vsim.wlf). This has the benefit of dumping all the signals (if your file was missing something, you'd have to rerun the simulation).

`timescale 1 ns / 1 ps

module tb_user();

  initial begin
    // Insert user code here, such as signal dumping
    // set CNY_PDK_TB_USER_VLOG variable in sim/makefile
`include "PDK_SIM_CONFIG.vh"
`ifdef AE0_PRESENT
`ifdef AE1_PRESENT
`ifdef AE2_PRESENT
`ifdef AE3_PRESENT


How to use UNISIM library in simulator?

Firstly, make sure to have your Coregen modules in the coregen/ folder in your PDK project. Then, navigate to the sim/ in your PDK project and execute the command:
vmap unisim /remote/Xilinx/13.4/ISE/vhdl/mti_se/10.1c/lin64/unisim/

Finally, you may want to include your module in your project's Makefile.include as follows:
USER_VHDL_FILES += ../coregen/fifo_64_1024.vhd

Emulator Related

How to read AEG registers in the emulator?

You can use the following function: uint64 AegRead(int aeId, int aegIdx);

How to read/write the memory in the emulator?

You can use the functions AeMemLoad and AeMemStore to read and write from/to the memory as follows:

bool AeMemLoad (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data);
bool AeMemStore (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data);

Also you can get mcId using the function McNum(addr)