Decapping Pictures

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Trial Runs

Below are images for the several different trial runs that we performed on three different Cyclone III FPGAs. Each of these three chips had a pocket milled out on the top of varying depth. More information can be found in the Acid Etching Documentation.

Trial 1: Cyclone III Mill Depth: 3/10 mm

  • Trial 1 was performed on the test chip with a 3/10mm pocket milled out in a 10x10mm square on the top of the chip. This trial shows what happens when the RFNA (Red Fuming Nitric Acid) is left on the chip for far too long.

Figure0.jpg Figure1.jpg Figure2.jpgFigure3.jpg Figure4.jpg Figure5.jpg

Trial 2: Cyclone III Mill Depth: 1/4 mm

  • Trial 2 was performed on the test chip with a 1/4mm pocket milled out in a 10x10mm square on the top of the chip. This trial had significantly better results than Trial 1. The entire die can be seen (ie. not eaten away by RFNA), and there looks to be a minimal amount of damage to both the bond wires and the die itself. There was a residual amount of packaging left on the die.

After 1 Minute of Die Exposed to RFNA

Trial2 1min .78x 1.jpg Trial2 1min 2.5x 1.jpg Trial2 1min 2.5x 2.jpg

After 2 Minutes of Die Exposed to RFNA

Trial2 2min .78x 1.jpg Trial2 2min 1.25x 1.jpg Trial2 2min 16x 1.jpg Trial2 2min 16x 2.jpg

After 3 Minutes of Die Exposed to RFNA

Trial2 3min .78x 1.jpg Trial2 3min 2.5x 1.jpg Trial2 3min 2.5x 2.jpg Trial2 3min 2.5x 3.jpg Trial2 3min 2.5x 4.jpg Trial2 3min 2.5x 5.jpg Trial2 3min 4x 1.jpg Trial2 3min 10x 1.jpg Trial2 3min 10x 2.jpg

Trial 3: Cyclone IV

  • Trial 3 was performed on two separate Cyclone IV FPGAs. They were both milled with a smaller, 4x4mm pocket on the top, with the first chip having a pocket depth of 0.2mm, and the second chip having a pocket depth of 0.125mm.

Cyclone IV: Mill depth: 1/5 mm

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Cyclone IV: Mill depth: 1/8 mm

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First Decapped Development Board

  • The first board that we decapped was the De0-nano development board. This board is based around the EP4CE22F17C6N FPGA, which is a Cyclone IV device with 22k Configurable Logic Blocks (CLBs). We decapped only a small window on the top of the chip, as we did not want to cut the bond wires as was done in Trial 3. The pocket milled in the top was a 2x2x0.125mm pocket, centered on the chip. The pictures shown below show the middle of the die which is where the arrays of CLBs are housed.

De0-Nano: Mill depth: 1/8 mm

DE0 nano 1.jpeg DE0 nano 2.jpeg DE0 nano 3.jpeg

Trial 4: Xilinx Zynq FPGA

  • The following pictures are the result of decapping three separate Xilinx Zynq FPGAs (XC7Z010). The milling depths ranged from 1/4 mm, to 1/8 mm, with a milling area of 10x10 mm.

Xilinx Zynq: 1/8mm

Xilinx Zynq: 1/5mm

Xilinx Zynq: 1/4mm