Difference between revisions of "Decapping Pictures"

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Below are images for the several different trial runs that we performed on three different Cyclone III FPGAs. Each of these three chips had a pocket milled out on the top of varying depth. More information can be found in the [[Acid Etching Documentation|Acid Etching Documentation]].
 
Below are images for the several different trial runs that we performed on three different Cyclone III FPGAs. Each of these three chips had a pocket milled out on the top of varying depth. More information can be found in the [[Acid Etching Documentation|Acid Etching Documentation]].
  
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===Trial 1===
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===Trial 1: Cyclone III Mill Depth: 3/10 mm===
−
*Trial 1 was performed on the test chip with a 3/10mm pocket milled out in a 10x10 square on the top of the chip. This trial shows what happens when the RFNA (Red Fuming Nitric Acid) is left on the chip for far too long.
+
*Trial 1 was performed on the test chip with a 3/10mm pocket milled out in a 10x10mm square on the top of the chip. This trial shows what happens when the RFNA (Red Fuming Nitric Acid) is left on the chip for far too long.
  
 
[[Image:Figure0.jpg|200px|frameless|border]] [[Image:Figure1.jpg|200px|frameless|border]] [[Image:Figure2.jpg|200px|frameless|border]][[Image:Figure3.jpg|200px|frameless]] [[Image:Figure4.jpg|200px|frameless|border]] [[Image:Figure5.jpg|200px|frameless|border]]
 
[[Image:Figure0.jpg|200px|frameless|border]] [[Image:Figure1.jpg|200px|frameless|border]] [[Image:Figure2.jpg|200px|frameless|border]][[Image:Figure3.jpg|200px|frameless]] [[Image:Figure4.jpg|200px|frameless|border]] [[Image:Figure5.jpg|200px|frameless|border]]
  
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===Trial 2===
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===Trial 2: Cyclone III Mill Depth: 1/4 mm===
−
*Trial 2 was performed on the test chip with a 1/4mm pocket milled out in a 10x10 square on the top of the chip. This trial had significantly better results than Trial 1. The entire die can be seen (ie. not eaten away by RFNA), and there looks to be a minimal amount of damage to both the bond wires and the die itself. There was a residual amount of packaging left on the die.
+
*Trial 2 was performed on the test chip with a 1/4mm pocket milled out in a 10x10mm square on the top of the chip. This trial had significantly better results than Trial 1. The entire die can be seen (ie. not eaten away by RFNA), and there looks to be a minimal amount of damage to both the bond wires and the die itself. There was a residual amount of packaging left on the die.
  
 
====After 1 Minute of Die Exposed to RFNA====
 
====After 1 Minute of Die Exposed to RFNA====
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====After 3 Minutes of Die Exposed to RFNA====
 
====After 3 Minutes of Die Exposed to RFNA====
 
[[Image:trial2_3min_.78x_1.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_1.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_2.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_3.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_4.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_5.jpg|200px|frameless|border]] [[Image:trial2_3min_4x_1.jpg|200px|frameless|border]] [[Image:trial2_3min_10x_1.jpg|200px|frameless|border]] [[Image:trial2_3min_10x_2.jpg|200px|frameless|border]]
 
[[Image:trial2_3min_.78x_1.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_1.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_2.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_3.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_4.jpg|200px|frameless|border]] [[Image:trial2_3min_2.5x_5.jpg|200px|frameless|border]] [[Image:trial2_3min_4x_1.jpg|200px|frameless|border]] [[Image:trial2_3min_10x_1.jpg|200px|frameless|border]] [[Image:trial2_3min_10x_2.jpg|200px|frameless|border]]
 +
 +
===Trial 3: Cyclone IV===
 +
*Trial 3 was performed on two separate Cyclone IV FPGAs. They were both milled with a smaller, 4x4mm pocket on the top, with the first chip having a pocket depth of 0.2mm, and the second chip having a pocket depth of 0.125mm.
 +
====Cyclone IV: Mill depth: 1/5 mm====
 +
[[Image:Trial3 cycloneIV 1 1.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 1 2.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 1 3.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 1 4.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 1 5.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 1 6.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 1 7.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 1 8.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 1 9.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 1 10.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 1 11.jpg|200px|frameless|border]]
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 +
====Cyclone IV: Mill depth: 1/8 mm====
 +
[[Image:Trial3 cycloneIV 2 1.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 2 2.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 2 3.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 2 4.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 2 5.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 2 6.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 2 7.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 2 8.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 2 9.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 2 10.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 2 11.jpg|200px|frameless|border]] [[Image:Trial3 cycloneIV 2 12.jpg|200px|frameless|border]]
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[[Image:Trial3 cycloneIV 2 13.jpg|200px|frameless|border]]
 +
 +
===First Decapped Development Board===
 +
*The first board that we decapped was the De0-nano development board. This board is based around the EP4CE22F17C6N FPGA, which is a Cyclone IV device with 22k Configurable Logic Blocks (CLBs). We decapped only a small window on the top of the chip, as we did not want to cut the bond wires as was done in Trial 3. The pocket milled in the top was a 2x2x0.125mm pocket, centered on the chip. The pictures shown below show the middle of the die which is where the arrays of CLBs are housed.
 +
 +
====De0-Nano: Mill depth: 1/8 mm====
 +
[[Image:DE0_nano_1.jpeg|200px|frameless|border]] [[Image:DE0_nano_2.jpeg|200px|frameless|border]] [[Image:DE0_nano_3.jpeg|200px|frameless|border]]
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 +
===Trial 4: Xilinx Zynq FPGA===
 +
*The following pictures are the result of decapping three separate Xilinx Zynq FPGAs (XC7Z010). The milling depths ranged from 1/4 mm, to 1/8 mm, with a milling area of 10x10 mm.
 +
 +
====Xilinx Zynq: 1/8mm====
 +
[[Image:0.125mm_xilinx_1.jpeg|200px|frameless|border]] [[Image:0.125mm_xilinx_2.jpeg|200px|frameless|border]] [[Image:0.125mm_xilinx_3.jpeg|200px|frameless|border]] [[Image:0.125mm_xilinx_4.jpeg|200px|frameless|border]] [[Image:0.125mm_xilinx_5.jpeg|200px|frameless|border]]
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====Xilinx Zynq: 1/5mm====
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[[Image:0.2mm_xilinx_1.jpeg|200px|frameless|border]] [[Image:0.20mm_xilinx_2.jpeg|200px|frameless|border]] [[Image:0.20mm_xilinx_3.jpeg|200px|frameless|border]] [[Image:0.20mm_xilinx_4.jpeg|200px|frameless|border]] [[Image:0.20mm_xilinx_5.jpeg|200px|frameless|border]] [[Image:0.20mm_xilinx_6.jpeg|200px|frameless|border]] [[Image:0.20mm_xilinx_7.jpeg|200px|frameless|border]]
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====Xilinx Zynq: 1/4mm====
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[[Image:0.25mm_xilinx_1.jpeg|200px|frameless|border]] [[Image:0.25mm_xilinx_2.jpeg|200px|frameless|border]] [[Image:0.25mm_xilinx_3.jpeg|200px|frameless|border]] [[Image:0.25mm_xilinx_4.jpeg|200px|frameless|border]] [[Image:0.25mm_xilinx_5.jpeg|200px|frameless|border]] [[Image:0.25mm_xilinx_6.jpeg|200px|frameless|border]] [[Image:0.25mm_xilinx_7.jpeg|200px|frameless|border]] [[Image:0.25mm_xilinx_8.jpeg|200px|frameless|border]] [[Image:0.25mm_xilinx_9.jpeg|200px|frameless|border]]
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===Second and Third De-capped development board===
 +
*The following pictures are from the de-capping of two separate development boards. It should be noted that BOTH boards were broken as a result of the decapping
 +
 +
====De0-Nano: 6x6x1/8mm====
 +
*The following pictures are a result of de-capping a De0-nano development board with milling surface area of 6x6mm. The milling area turned out to be roughly the size of the die, thus resulting in many bond wires being severed
 +
 +
[[Image:De0_6x6_1.jpg|200px|frameless|border]] [[Image:De0_6x6_2.jpg|200px|frameless|border]] [[Image:De0_6x6_3.jpg|200px|frameless|border]] [[Image:De0_6x6_4.jpg|200px|frameless|border]]
 +
 +
====Zybo: 7x5x1/8mm====
 +
*The following pictures are a result of de-capping a Digilent Zybo development board with a milling surface area of 7x5mm. This milling area is the size of the die itself for the Xilinx Zynq SoC. We chose to mill the entire die because previous trials with the Zynq chip showed that the bonding and connecting of wires to the BGA pins is significantly different than for the Altera chips.
 +
 +
[[Image:Zybo_7x5_1.jpg|200px|frameless|border]] [[Image:Zybo_7x5_2.jpg|200px|frameless|border]] [[Image:Zybo_7x5_3.jpg|200px|frameless|border]] [[Image:Zybo_7x5_4.jpg|200px|frameless|border]]

Latest revision as of 11:34, 31 March 2014

Trial Runs

Below are images for the several different trial runs that we performed on three different Cyclone III FPGAs. Each of these three chips had a pocket milled out on the top of varying depth. More information can be found in the Acid Etching Documentation.

Trial 1: Cyclone III Mill Depth: 3/10 mm

  • Trial 1 was performed on the test chip with a 3/10mm pocket milled out in a 10x10mm square on the top of the chip. This trial shows what happens when the RFNA (Red Fuming Nitric Acid) is left on the chip for far too long.

Figure0.jpg Figure1.jpg Figure2.jpgFigure3.jpg Figure4.jpg Figure5.jpg

Trial 2: Cyclone III Mill Depth: 1/4 mm

  • Trial 2 was performed on the test chip with a 1/4mm pocket milled out in a 10x10mm square on the top of the chip. This trial had significantly better results than Trial 1. The entire die can be seen (ie. not eaten away by RFNA), and there looks to be a minimal amount of damage to both the bond wires and the die itself. There was a residual amount of packaging left on the die.

After 1 Minute of Die Exposed to RFNA

Trial2 1min .78x 1.jpg Trial2 1min 2.5x 1.jpg Trial2 1min 2.5x 2.jpg

After 2 Minutes of Die Exposed to RFNA

Trial2 2min .78x 1.jpg Trial2 2min 1.25x 1.jpg Trial2 2min 16x 1.jpg Trial2 2min 16x 2.jpg

After 3 Minutes of Die Exposed to RFNA

Trial2 3min .78x 1.jpg Trial2 3min 2.5x 1.jpg Trial2 3min 2.5x 2.jpg Trial2 3min 2.5x 3.jpg Trial2 3min 2.5x 4.jpg Trial2 3min 2.5x 5.jpg Trial2 3min 4x 1.jpg Trial2 3min 10x 1.jpg Trial2 3min 10x 2.jpg

Trial 3: Cyclone IV

  • Trial 3 was performed on two separate Cyclone IV FPGAs. They were both milled with a smaller, 4x4mm pocket on the top, with the first chip having a pocket depth of 0.2mm, and the second chip having a pocket depth of 0.125mm.

Cyclone IV: Mill depth: 1/5 mm

Trial3 cycloneIV 1 1.jpg Trial3 cycloneIV 1 2.jpg Trial3 cycloneIV 1 3.jpg Trial3 cycloneIV 1 4.jpg Trial3 cycloneIV 1 5.jpg Trial3 cycloneIV 1 6.jpg Trial3 cycloneIV 1 7.jpg Trial3 cycloneIV 1 8.jpg Trial3 cycloneIV 1 9.jpg Trial3 cycloneIV 1 10.jpg Trial3 cycloneIV 1 11.jpg

Cyclone IV: Mill depth: 1/8 mm

Trial3 cycloneIV 2 1.jpg Trial3 cycloneIV 2 2.jpg Trial3 cycloneIV 2 3.jpg Trial3 cycloneIV 2 4.jpg Trial3 cycloneIV 2 5.jpg Trial3 cycloneIV 2 6.jpg Trial3 cycloneIV 2 7.jpg Trial3 cycloneIV 2 8.jpg Trial3 cycloneIV 2 9.jpg Trial3 cycloneIV 2 10.jpg Trial3 cycloneIV 2 11.jpg Trial3 cycloneIV 2 12.jpg Trial3 cycloneIV 2 13.jpg

First Decapped Development Board

  • The first board that we decapped was the De0-nano development board. This board is based around the EP4CE22F17C6N FPGA, which is a Cyclone IV device with 22k Configurable Logic Blocks (CLBs). We decapped only a small window on the top of the chip, as we did not want to cut the bond wires as was done in Trial 3. The pocket milled in the top was a 2x2x0.125mm pocket, centered on the chip. The pictures shown below show the middle of the die which is where the arrays of CLBs are housed.

De0-Nano: Mill depth: 1/8 mm

DE0 nano 1.jpeg DE0 nano 2.jpeg DE0 nano 3.jpeg

Trial 4: Xilinx Zynq FPGA

  • The following pictures are the result of decapping three separate Xilinx Zynq FPGAs (XC7Z010). The milling depths ranged from 1/4 mm, to 1/8 mm, with a milling area of 10x10 mm.

Xilinx Zynq: 1/8mm

0.125mm xilinx 1.jpeg 0.125mm xilinx 2.jpeg 0.125mm xilinx 3.jpeg 0.125mm xilinx 4.jpeg 0.125mm xilinx 5.jpeg

Xilinx Zynq: 1/5mm

0.2mm xilinx 1.jpeg 0.20mm xilinx 2.jpeg 0.20mm xilinx 3.jpeg 0.20mm xilinx 4.jpeg 0.20mm xilinx 5.jpeg 0.20mm xilinx 6.jpeg 0.20mm xilinx 7.jpeg

Xilinx Zynq: 1/4mm

0.25mm xilinx 1.jpeg 0.25mm xilinx 2.jpeg 0.25mm xilinx 3.jpeg 0.25mm xilinx 4.jpeg 0.25mm xilinx 5.jpeg 0.25mm xilinx 6.jpeg 0.25mm xilinx 7.jpeg 0.25mm xilinx 8.jpeg 0.25mm xilinx 9.jpeg

Second and Third De-capped development board

  • The following pictures are from the de-capping of two separate development boards. It should be noted that BOTH boards were broken as a result of the decapping

De0-Nano: 6x6x1/8mm

  • The following pictures are a result of de-capping a De0-nano development board with milling surface area of 6x6mm. The milling area turned out to be roughly the size of the die, thus resulting in many bond wires being severed

De0 6x6 1.jpg De0 6x6 2.jpg De0 6x6 3.jpg De0 6x6 4.jpg

Zybo: 7x5x1/8mm

  • The following pictures are a result of de-capping a Digilent Zybo development board with a milling surface area of 7x5mm. This milling area is the size of the die itself for the Xilinx Zynq SoC. We chose to mill the entire die because previous trials with the Zynq chip showed that the bonding and connecting of wires to the BGA pins is significantly different than for the Altera chips.

Zybo 7x5 1.jpg Zybo 7x5 2.jpg Zybo 7x5 3.jpg Zybo 7x5 4.jpg

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