Main Page

Welcome to the Reconfigurable Computing wiki.

GPGPU Sim

• How To: Checkout the Project and Make

FPGA Design Flow

Xilinx Resources

• Spartan6 CLB Guide
• Spartan6-specific HDL primitives
• Spartan3-specific HDL primitives
• Xilinx Constraints Guide

Command-line Processing

• Digilent board config tool
  • Presents a command line alternative to Adept
• Xilinx Command Line Tools Users Guide
  • Any process you run in ISE can also be automated from the command line!
• FPGA_Edline
  • Scripted editing can be performed through the command line version of FPGA Editor

FPGA Editor Tasks

• Creating Hard Macros

SDIR=`dirname "$BASH_SOURCE"`
CDIR=`readlink -f "$SDIR"`

export XLNX_VER=14.5
export VVDO_VER=2013.1
export ALTR_VER=12.0
export ARCH_VER=64
export VSIM_VER=10.1c

printf "Setting up environment variables for %s-bit Xilinx ISE tools, version %s..." $ARCH_VER $XLNX_VER
source /remote/Xilinx/$XLNX_VER/settings$ARCH_VER.sh
printf "done.\n"

printf "Setting up environment variables for %s-bit Xilinx Vivado tools, version %s..." $ARCH_VER $VVDO_VER
source /remote/Xilinx/$VVDO_VER/settings$ARCH_VER.sh
printf "done.\n"

printf "Setting up path for %s-bit Modelsim tools, version %s..." $ARCH_VER $VSIM_VER
export PATH=$PATH:/remote/Modelsim/$VSIM_VER/modeltech/linux_x86_64/
printf "done.\n"

printf "Setting up environment variables for %s-bit Altera tools, version %s..." $ARCH_VER $ALTR_VER
export PATH=$PATH:/remote/Altera/$ALTR_VER/quartus/bin
printf "done.\n"

printf "Setting up license file..."
export LM_LICENSE_FILE=2201@mitch.ece.iastate.edu:1717@io.ece.iastate.edu:27006@io.ece.iastate.edu
printf "done.\n"