Using AXI Monitor: Difference between revisions
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These instructions are geared towards using the Chipscope with a Zynq 7000 chip in mind, but in general it can be applied to nearly any Xilinx FPGA. It's also assuming that development is done on one of the Linux servers, connecting to the Zedboard using the hw_server tool (as in the CprE488 labs) | ==Assumptions== | ||
These instructions are geared towards using the Chipscope with a Zynq 7000 chip in mind, but in general it can be applied to nearly any Xilinx FPGA. It's also assuming that development is done on one of the Linux servers, connecting to the Zedboard using the hw_server tool (as in the CprE488 labs). Programming the bitfile, the *.elf software binary, and Chipscope monitoring are all done over the running hw_server. | |||
==Necessary IP Blocks== | |||
There are two IP blocks which need to be added to the project. Here we're using XPS, but these could be added in a regular ISE project too. | There are two IP blocks which need to be added to the project. Here we're using XPS, but these could be added in a regular ISE project too. | ||
* Chipscope Integrated Controller | * Chipscope Integrated Controller: interfaces between JTAG and one or more Chipscope monitors. | ||
* Chipscope AXI Monitor | * Chipscope AXI Monitor: listens to a single AXI bus. | ||
Consider the XPS screenshot below. We search for "chip" in the IP catalog and add the two cores mentioned earlier. These are added as '''chipscope_icon_0''' and '''chipscope_axi_monitor_0'''. The '''chipscope_icon_0''' has a port '''monitor0''' which is connected to '''chipscope_icon_0::CHIPSCOPE_ICON_CONTROL'''. The '''chipscope_axi_monitor_0''' has a port '''MON_AXI''' which is connected to the only AXI bus in the design, called '''axi_interconnect_1'''. | |||
<br/>[[Image:Screenshot1.png]] | <br/>[[Image:Screenshot1.png]] | ||
Build the bitfile and export to SDK as usual. | |||
==Using Chipscope== | |||
In Windows (ie the system attached to the Zedboard), load Chipscope: | |||
TODO | |||
Revision as of 05:47, 4 December 2014
Assumptions
These instructions are geared towards using the Chipscope with a Zynq 7000 chip in mind, but in general it can be applied to nearly any Xilinx FPGA. It's also assuming that development is done on one of the Linux servers, connecting to the Zedboard using the hw_server tool (as in the CprE488 labs). Programming the bitfile, the *.elf software binary, and Chipscope monitoring are all done over the running hw_server.
Necessary IP Blocks
There are two IP blocks which need to be added to the project. Here we're using XPS, but these could be added in a regular ISE project too.
- Chipscope Integrated Controller: interfaces between JTAG and one or more Chipscope monitors.
- Chipscope AXI Monitor: listens to a single AXI bus.
Consider the XPS screenshot below. We search for "chip" in the IP catalog and add the two cores mentioned earlier. These are added as chipscope_icon_0 and chipscope_axi_monitor_0. The chipscope_icon_0 has a port monitor0 which is connected to chipscope_icon_0::CHIPSCOPE_ICON_CONTROL. The chipscope_axi_monitor_0 has a port MON_AXI which is connected to the only AXI bus in the design, called axi_interconnect_1.
Build the bitfile and export to SDK as usual.
Using Chipscope
In Windows (ie the system attached to the Zedboard), load Chipscope:
TODO