Using AXI Monitor - Revision history

Ajmills: /* Using Chipscope */

2014-12-07T02:58:32Z

Using Chipscope

← Older revision		Revision as of 02:58, 7 December 2014
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	In Windows (ie the system attached to the Zedboard), load Chipscope:		In Windows (ie the system attached to the Zedboard), load Chipscope:

	~~TODO~~		* Click JTAG Chain -> Open Plugin ...
			* Select the item that contains "Xilinx_platformusb", click OK.
			* The software will connect over JTAG. Click OK on the next dialog.
			* A window comes up which will contain the waveform data, but all the signals are called "DataPort[x]". We need to tell Chipscope the signal names.
			** Click File -> Import...
			** Click '''Select New File''' and browse to the .cdc file. This will be in something like ''project/implementation/chipscope_axi_monitor_0_wrapper/chipscope_axi_monitor_0.cdc''. Leave the rest default and click OK.
			* Set up the trigger in the "Trigger Setup" window. For example:
			** Set up a trigger address in M0:MON_AXI_ARADDR
			** Open M1:MON_AXI_ARADDRCONTROL and put a 1 for the value of MON_AXI_RVALID.
			** Set the Trigger Condition Equation to '''M0 && M1'''
			* Click the "Play" icon in the toolbar to arm the trigger.
			* Click the Green "P" button on the toolbar to disable polling. '''If polling is enabled you cannot program the device'''/
			* In XSDK program the device as normal. After the program terminates, click the "P" button in Chipscope to turn polling back on to pull in the waveform data that was triggered on (assuming there is any). Note that polling must be turned off again before each time you program the chip.

Ajmills at 05:47, 4 December 2014

2014-12-04T05:47:52Z

← Older revision		Revision as of 05:47, 4 December 2014
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	These instructions are geared towards using the Chipscope with a Zynq 7000 chip in mind, but in general it can be applied to nearly any Xilinx FPGA. It's also assuming that development is done on one of the Linux servers, connecting to the Zedboard using the hw_server tool (as in the CprE488 labs)		==Assumptions==

			These instructions are geared towards using the Chipscope with a Zynq 7000 chip in mind, but in general it can be applied to nearly any Xilinx FPGA. It's also assuming that development is done on one of the Linux servers, connecting to the Zedboard using the hw_server tool (as in the CprE488 labs). Programming the bitfile, the *.elf software binary, and Chipscope monitoring are all done over the running hw_server.

			==Necessary IP Blocks==

	There are two IP blocks which need to be added to the project. Here we're using XPS, but these could be added in a regular ISE project too.		There are two IP blocks which need to be added to the project. Here we're using XPS, but these could be added in a regular ISE project too.

	* Chipscope Integrated Controller		* Chipscope Integrated Controller: interfaces between JTAG and one or more Chipscope monitors.
	* Chipscope AXI Monitor		* Chipscope AXI Monitor: listens to a single AXI bus.

			Consider the XPS screenshot below. We search for "chip" in the IP catalog and add the two cores mentioned earlier. These are added as '''chipscope_icon_0''' and '''chipscope_axi_monitor_0'''. The '''chipscope_icon_0''' has a port '''monitor0''' which is connected to '''chipscope_icon_0::CHIPSCOPE_ICON_CONTROL'''. The '''chipscope_axi_monitor_0''' has a port '''MON_AXI''' which is connected to the only AXI bus in the design, called '''axi_interconnect_1'''.

	<br/>[[Image:Screenshot1.png]]		<br/>[[Image:Screenshot1.png]]

			Build the bitfile and export to SDK as usual.

			==Using Chipscope==

			In Windows (ie the system attached to the Zedboard), load Chipscope:

			TODO

Ajmills at 05:32, 4 December 2014

2014-12-04T05:32:45Z

← Older revision		Revision as of 05:32, 4 December 2014
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	* Chipscope AXI Monitor		* Chipscope AXI Monitor

	<br/>[[Image:~~XPS Screeenshot1~~.png]]		<br/>[[Image:Screenshot1.png]]

Ajmills at 05:31, 4 December 2014

2014-12-04T05:31:59Z

← Older revision		Revision as of 05:31, 4 December 2014
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	There are two IP blocks which need to be added to the project. Here we're using XPS, but these could be added in a regular ISE project too.		There are two IP blocks which need to be added to the project. Here we're using XPS, but these could be added in a regular ISE project too.

	* Chipscope Integrated Controller ~~("chipscope_icon")~~		* Chipscope Integrated Controller
	* Chipscope AXI Monitor		* Chipscope AXI Monitor

			<br/>[[Image:XPS Screeenshot1.png]]

Ajmills: New page: These instructions are geared towards using the Chipscope with a Zynq 7000 chip in mind, but in general it can be applied to nearly any Xilinx FPGA. It's also assuming that development is ...

2014-12-04T05:19:43Z

New page: These instructions are geared towards using the Chipscope with a Zynq 7000 chip in mind, but in general it can be applied to nearly any Xilinx FPGA. It's also assuming that development is ...

New page

These instructions are geared towards using the Chipscope with a Zynq 7000 chip in mind, but in general it can be applied to nearly any Xilinx FPGA. It's also assuming that development is done on one of the Linux servers, connecting to the Zedboard using the hw_server tool (as in the CprE488 labs)

There are two IP blocks which need to be added to the project. Here we're using XPS, but these could be added in a regular ISE project too.

* Chipscope Integrated Controller ("chipscope_icon")
* Chipscope AXI Monitor