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• 00:14, 12 February 2013 Ogamal talk contribs uploaded File:Vhd2v isnt.txt (Simple script to read a VHDL module and generate code to instantiate it in Verilog NOTE: change script name to "vhd2v_inst.py" first then run as: "python vhd2v_inst.py <filename.vhd>")