Using System Verilog files in your Project

System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently). XST (simulator) does not support System Verilog.

You'll need to add a few flags to the compilers to support System Verilog. Open the main project make file (Makefile.include) and add:

 VERILOG_COMPILE_OPTIONS += -mfcu -sv