Using System Verilog files in your Project

System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently).

You'll need to add a few flags to the compilers to support System Verilog. Open the main project make file (Makefile.include) and add:

 VERILOG_COMPILE_OPTIONS += -mfcu -sv

Unfortunately, XST (Xilinx Synthesis Tool for creating bitfiles) won't support System Verilog until a (ever increasing) newer version. 3rd party ($$$) tools are required.