Frequently Asked Questions

General FAQ

How to add new verilog files or directories to a PDK project?

By default, the PDK looks like the project/verilog directory and compiles all .v files found there. To add other Verilog directories, use this makefile variable:
USER_VERILOG_DIRS += ../../verilog

How to run Modelsim GUI while simulating?

You may run the simulation in interactive mode by adding the following line to the makefile in the sim directory:

USER_SIM_OPTIONS = -gui

Another option is to edit the test bench (sim/tb_user.v shown below) to dump the waveforms to a file, then run the hardware simulator via command line, and finally open up the waveform file (vsim -v ./sim/vsim.wlf). This has the benefit of dumping all the signals (if your wave.do file was missing something, you'd have to rerun the simulation).

`timescale 1 ns / 1 ps

module tb_user();

  initial begin
    // Insert user code here, such as signal dumping
    // set CNY_PDK_TB_USER_VLOG variable in sim/makefile
`include "PDK_SIM_CONFIG.vh"
`ifdef AE0_PRESENT
    $wlfdumpvars(5,testbench.cae_fpga0.ae_top.core.cae_pers);
`endif
`ifdef AE1_PRESENT
    $wlfdumpvars(5,testbench.cae_fpga1.ae_top.core.cae_pers);
`endif
`ifdef AE2_PRESENT
    $wlfdumpvars(5,testbench.cae_fpga2.ae_top.core.cae_pers);
`endif
`ifdef AE3_PRESENT
    $wlfdumpvars(5,testbench.cae_fpga3.ae_top.core.cae_pers);
`endif
  end

endmodule

Emulator Related

How to read AEG registers in the emulator?

You can use the following function: uint64 AegRead(int aeId, int aegIdx);

How to read/write the memory in the emulator?

You can use the functions AeMemLoad and AeMemStore to read and write from/to the memory as follows:

bool AeMemLoad (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data);
bool AeMemStore (int aeId, int mcId, unint64 addr, int size, bool bSigned, uint64 &data);