Adding VHDL Files to a Project: Difference between revisions
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== Option 1 == | == Using Your VHDL Module In The Top Level cae_pers.v File== | ||
== Include Option 1 == | |||
Use the USER_VHDL_FILES variable in the project makefile: | Use the USER_VHDL_FILES variable in the project makefile: | ||
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The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled. | The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled. | ||
== Option 1.1 == | == Include Option 1.1 == | ||
Use the USER_VHDL_FILES variable in the project's top level Makefile.include: | Use the USER_VHDL_FILES variable in the project's top level Makefile.include: | ||
USER_VHDL_FILES += ../vhdl/file.vhd | USER_VHDL_FILES += ../vhdl/file.vhd | ||
*Still use the ../ because this path will get included in the lower level directories, and the makefile there will still expect a relative path. | |||
== Option 2 == | == Include Option 2 == | ||
Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile: | Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile: | ||
Revision as of 22:24, 2 February 2013
Using Your VHDL Module In The Top Level cae_pers.v File
Include Option 1
Use the USER_VHDL_FILES variable in the project makefile:
USER_VHDL_FILES += file1.vhd file2.vhd
The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.
Include Option 1.1
Use the USER_VHDL_FILES variable in the project's top level Makefile.include:
USER_VHDL_FILES += ../vhdl/file.vhd
- Still use the ../ because this path will get included in the lower level directories, and the makefile there will still expect a relative path.
Include Option 2
Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:
CNY_PDK_USER_DIRECTORY CNY_PDK_SITE_DIRECTORY
This is a good place to set which simulator you use, set up signal tracing, etc.
Other information
There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.