Team 142875: Difference between revisions
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2 Evaluate Hardware Options | 2 Evaluate Hardware Options | ||
3 Define Custom Instructions | 3 Define Custom Instructions | ||
* The functions implemented by the hardware design can then be mapped to custom instructions. | * The functions implemented by the hardware design can then be mapped to custom instructions. | ||
| Line 19: | Line 20: | ||
* Convey provides an architecture simulation environment to allow rapid prototyping of both the hardware and software components of a custom personality. | * Convey provides an architecture simulation environment to allow rapid prototyping of both the hardware and software components of a custom personality. | ||
* This environment is written in C++ to emulate the rest of the system. It includes hardware models of instruction dispatch, register state and the memory subsystem. | * This environment is written in C++ to emulate the rest of the system. It includes hardware models of instruction dispatch, register state and the memory subsystem. | ||
5 Modify Application to Use Coprocessor | |||
6 Compile Application with Convey Compiler | |||
7 Simulate Application with Convey Architecture Simulator | |||
* This step allows the application and the custom instruction set to be debugged before the hardware is designed. | |||
8 Develop FPGA Hardware | |||
9 Simulate Hardware in Convey Simulation Environment | |||
* Convey provides a hardware simulation environment with bus-functional models for all hardware interfaces to the Application Engine (AE) FPGA. | |||
Using a standard VPI interface (Verilog Procedural Inteface) the architecture simulator can be used to provide stimulus to the HDL simulation. | |||
10 Integrate with Convey Hardware | |||
Revision as of 15:46, 1 February 2012
Team members
- Michael Patterson
- Chetan N-Govindaiah
- Jungmin Park
Assignment 1
Developing a Custom Personality
1 Analyze Application
- How does the current application perform on existing hardware?
- What bottleneacks are limiting the performance?
- What data structures are involved?
- How parallelizable is the application?
2 Evaluate Hardware Options
3 Define Custom Instructions
- The functions implemented by the hardware design can then be mapped to custom instructions.
4 Develop Software Model of Custom Personality
- Convey provides an architecture simulation environment to allow rapid prototyping of both the hardware and software components of a custom personality.
- This environment is written in C++ to emulate the rest of the system. It includes hardware models of instruction dispatch, register state and the memory subsystem.
5 Modify Application to Use Coprocessor
6 Compile Application with Convey Compiler
7 Simulate Application with Convey Architecture Simulator
- This step allows the application and the custom instruction set to be debugged before the hardware is designed.
8 Develop FPGA Hardware
9 Simulate Hardware in Convey Simulation Environment
- Convey provides a hardware simulation environment with bus-functional models for all hardware interfaces to the Application Engine (AE) FPGA.
Using a standard VPI interface (Verilog Procedural Inteface) the architecture simulator can be used to provide stimulus to the HDL simulation. 10 Integrate with Convey Hardware
Running the Sample Application []
1. Copy Sample AE and Sample Application The Vadd sample personality and application is installed with the PDK RPM in /opt/convey/pdk/2010_08_09/.
The sample is made up of two components:
- cae_pers_vadd - contains the sample custom personality, including the software model which emulates the Application Engine FPGA
- SampleAppVadd - contains the application that uses the instruction defined in the CasSample tree.
cd $HOME mkdir pdk_sample cp -r /opt/convey/pdk/2010_08_09/cae_sample_vadd pdk_sample cp -r /opt/convey/pdk/2010_08_09/pdk_apps/SampleAppVadd pdk_sample
2. Build the Sample AE and Sample Application
cd $HOME/pdk_sample/cae_pers_vadd/CaeSim make cd ../../SampleAppVadd make ./UserApp.exe