Using the Memory Controller Interface: Difference between revisions

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New page: == Memory Controller Interface functionality == * Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface. * Each of the 8 MC interf...
 
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* The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
* The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
* Each of the even and odd ports has its request signals and response signals.
* Each of the even and odd ports has its request signals and response signals.
* Refer to section 9.3.3.1 about how read and write operations work.
* Refer to section 9.3.3.1 in the PDK for further informations.


== Memory Controller Interface Signals ==
== Memory Controller Interface Signals ==
The 4<super>th</super> MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7.
The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port are appended with <code>_e</code> and the signals for the odd port are appended with <code>_o</code>
 
{| border="1" class="wikitable" style="border-collapse:collapse;"
{| border="1" class="wikitable" style="border-collapse:collapse;"
|-
|-
! Even Port
! Even Port || Odd Port
|-
|-
| mc4_req_ld_e
| mc4_req_ld_e || mc4_req_ld_o
|-
|-
| mc4_req_st_e
| mc4_req_st_e || mc4_req_st_o
|-
|-
| mc4_req_size_e<1:0>
| mc4_req_size_e<1:0> || mc4_req_size_o<1:0>
|-
|-
| mc4_req_vadr_e<47:0>
| mc4_req_vadr_e<47:0> || mc4_req_vadr_o<47:0>
|-
|-
| mc4_req_wrd_rdctl_e<63:0>
| mc4_req_wrd_rdctl_e<63:0> || mc4_req_wrd_rdctl_o<63:0>
|-
|-
| mc4_req_flush_e
| mc4_req_flush_e || mc4_req_flush_o
|-
|-
| mc4_rd_rq_stall_e
| mc4_rd_rq_stall_e || mc4_rd_rq_stall_o
|-
|-
| mc4_wr_rq_stall_e
| mc4_wr_rq_stall_e || mc4_wr_rq_stall_o
|-
|-
! Odd Port
| mc4_rsp_push_e || mc4_rsp_push_o
|-
|-
| mc4_req_ld_o
| mc4_rsp_stall_e || mc4_rsp_stall_o
|-
|-
| mc4_req_st_o
| mc4_rsp_data_e<63:0> || mc4_rsp_data_o<63:0>
|-
|-
| mc4_req_size_o<1:0>  
| mc4_rsp_rdctl_e<31:0> || mc4_rsp_rdctl_o<31:0>
|-
|-
| mc4_req_vadr_o<47:0>
| mc4_rsp_flush_cmplt_e || mc4_rsp_flush_cmplt_o
|-
| mc4_req_wrd_rdctl_o<63:0>
|-
| mc4_req_flush_o
|-
| mc4_rd_rq_stall_o
|-
| mc4_wr_rq_stall_o
|}
|}
== Reading from Memory ==
To read from memory, you have to assert the signal <code>mci_req_ld_x</code> and put the address of the data you want to read on the port <code>mci_req_vadr_x</code>. <code>i</code> is the MC interface port number and <code>x</code> is changed in case of even or odd port.
== Writing to Memory ==

Revision as of 23:11, 5 February 2013

Memory Controller Interface functionality

  • Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface.
  • Each of the 8 MC interfaces consists of two 150MHz ports (odd port and even port). So, the MC interface contains a total of 16 port.
  • The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
  • Each of the even and odd ports has its request signals and response signals.
  • Refer to section 9.3.3.1 in the PDK for further informations.

Memory Controller Interface Signals

The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port are appended with _e and the signals for the odd port are appended with _o

Even Port Odd Port
mc4_req_ld_e mc4_req_ld_o
mc4_req_st_e mc4_req_st_o
mc4_req_size_e<1:0> mc4_req_size_o<1:0>
mc4_req_vadr_e<47:0> mc4_req_vadr_o<47:0>
mc4_req_wrd_rdctl_e<63:0> mc4_req_wrd_rdctl_o<63:0>
mc4_req_flush_e mc4_req_flush_o
mc4_rd_rq_stall_e mc4_rd_rq_stall_o
mc4_wr_rq_stall_e mc4_wr_rq_stall_o
mc4_rsp_push_e mc4_rsp_push_o
mc4_rsp_stall_e mc4_rsp_stall_o
mc4_rsp_data_e<63:0> mc4_rsp_data_o<63:0>
mc4_rsp_rdctl_e<31:0> mc4_rsp_rdctl_o<31:0>
mc4_rsp_flush_cmplt_e mc4_rsp_flush_cmplt_o


Reading from Memory

To read from memory, you have to assert the signal mci_req_ld_x and put the address of the data you want to read on the port mci_req_vadr_x. i is the MC interface port number and x is changed in case of even or odd port.

Writing to Memory