Using System Verilog files in your Project: Difference between revisions
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System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently) | System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently). | ||
You'll need to add a few flags to the compilers to support System Verilog. Open the main project make file (Makefile.include) and add: | You'll need to add a few flags to the compilers to support System Verilog. Open the main project make file (Makefile.include) and add: | ||
Latest revision as of 05:04, 20 September 2012
System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently).
You'll need to add a few flags to the compilers to support System Verilog. Open the main project make file (Makefile.include) and add:
VERILOG_COMPILE_OPTIONS += -mfcu -sv
Unfortunately, XST (Xilinx Synthesis Tool for creating bitfiles) won't support System Verilog until a (ever increasing) newer version. 3rd party ($$$) tools are required.