Adding VHDL Files to a Project

Using Your VHDL Module In The Top Level cae_pers.v File

Entity Definition

entity test is
port(
     in1 : in std_logic;
     in2 : in std_logic;
     out1: out std_logic);
end entity;

Instantiation in Verilog

• It will look exactly like any other module instantiation in Verilog.

test t1(
     .in1(myInput),
     .in2(myOtherInput),
     .out(myOutput)
     );

• Another easier way is to use this Python script to generate instantiation code in Verilog. Use the following command:

$ source cnyEnv
$ mv ./vhd2v_inst.txt /.vhd2v_isnt.py
$ ./vhd2v_inst.py <filename>

Module With Vectors

• If we change the earlier definition to look like the following

entity testWithVector is
port(
     in1 : in std_logic_vector(63 downto 0);
     in2 : in std_logic_vector(63 downto 0);
     out1: out std_logic);
end entity;

• Notice that the expected input is a 64 bit wide signal path
• Assume that you have a Verilog reg as follows

reg [63:0] myReg;
reg [63:0] myOtherReg;

• Modlesim will let you directly map myReg to in1 or in2 (see below), however ISE will generally fail to compile this code, with an error about the expected size being incorrect

test t1(
     .in1(myReg),
     .in2(myOtherReg),
     .out(myOutput)
     );

• The easiest way around this is to map myReg to a wire, and use that in the instantiation of your VHDL module

wire [63:0] wire_myReg;
wire [63:0] wire_myOtherReg;
assign wire_myReg = myReg;
assign wire_myOtherReg = myOtherReg;

test t1(
     .in1(wire_myReg),
     .in2(wire_myOtherReg),
     .out(myOutput)
     );

Include Option 1

Use the USER_VHDL_FILES variable in the project makefile:

USER_VHDL_FILES += file1.vhd file2.vhd

The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

Include Option 1.1

Use the USER_VHDL_FILES variable in the project's top level Makefile.include:

USER_VHDL_FILES += ../vhdl/file.vhd

• Still use the ../ because this path will get included in the lower level directories, and the makefile there will still expect a relative path.

Include Option 2

Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

CNY_PDK_USER_DIRECTORY CNY_PDK_SITE_DIRECTORY

This is a good place to set which simulator you use, set up signal tracing, etc.

Other information

There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.