Team Blitz: Difference between revisions

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* Parth Malkan
* Parth Malkan
* Rashmi Girmal
* Rashmi Girmal
* Shashank Reddy
* Joy Shukla
* Joy Shukla
* Utkarsh Gupta
* Utkarsh Gupta
==Velvet Genome Assembly Algorithm==
*Velvet Algorithm
:*[[Media:Velvet_Bruijn_graphs_2008.pdf | Reference Paper]]
:*[[Media:velvet_poster.pdf | Poster]]
:*[[Media:Blitz_week8.pdf | Presentation]]
:*[[Media:1015333.pdf | Velvet Implementation on Convey]]
*Links to Velvet Material
:*[http://genome.cshlp.org/content/18/5/821.long Journal Article]
:*[http://www.ebi.ac.uk/~zerbino/velvet/ Latest Version of Velvet software available for download]
*Parallelizing Velvet Algorithm
:*[[Media:1569511963.pdf | Reference Paper]]
:*[[Media:Blitz_week9.pdf | Presentation]]


== Wiki Contributions ==
== Wiki Contributions ==
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*Joy and Rashmi
*Joy and Rashmi
  [[Media:02-CUDA_basic.pdf | CUDA Basics]]
 
  [[Media:Convey_HC-2_Architectual_Overview.pdf | Convey HC-2 Architectural Overview]]
:*Week 1
Week 2
::* [[Media:02-CUDA_basic.pdf | CUDA Basics]]
  [[Media:block_diag_vadd.jpg | Vector adder basic block diagram]]
::* [[Media:Convey_HC-2_Architectual_Overview.pdf | Convey HC-2 Architectural Overview]]
  [http://numato.com/learning-fpga-and-verilog-a-beginners-guide-part-2-modules | Verilog tutorial for beginners]
:*Week 2
::* [[Media:block_diag_vadd.jpg | Vector adder basic block diagram]]
::* [http://numato.com/learning-fpga-and-verilog-a-beginners-guide-part-2-modules Verilog tutorial for beginners]
:*Week 3 
::* [[Media:ConveyTutorial1_modified.pdf | Updated Convey PDK Tutorial]]
::* [http://www.asic-world.com/verilog/verilog_one_day.html  Verilog in one day]
:*Week 5
::* [[Media:mc_array10.jpg | FSM for reading an array from memory given the address of the array]]
 
*Utkarsh
:*Week 1
::* [[Media:High-Performance Heterogeneous Computing with the Convey HC-1.pdf | High Performance Heterogeneous Computing with the Convey HC-1]]
::* [[Media:Iowa-State-University-2012-MemoCODE-Conference-design-contest-exact-match-short-read-aligner.pdf | Iowa State University 2012 MemoCODE]]
:*Week 2
::* [[Media:01-LanguageWhitePaper.pdf‎ | Difference between VHDL, Verilog and SystemVerilog]]
:*Week 6 
::* [[Media:PR_Broad.pdf‎ | Convey HC in Genome Sequencing]]
:*Week 10
::* [[Media:Nelson_T_0_0_2000_Implementa.pdf | IMPLEMENTATION OF IMAGE PROCESSING ALGORITHMS ON FPGA HARDWARE]]

Latest revision as of 07:23, 12 May 2013