Using System Verilog files in your Project: Difference between revisions
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New page: System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently). XST (simulator) does not support System Verilog. You'll need to add a few flags to the compi... |
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Revision as of 22:51, 19 September 2012
System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently). XST (simulator) does not support System Verilog.
You'll need to add a few flags to the compilers to support System Verilog. Open the main project make file (Makefile.include) and add:
VERILOG_COMPILE_OPTIONS += -mfcu -sv