Information for "Using System Verilog files in your Project"
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Basic information
| Display title | Using System Verilog files in your Project |
| Default sort key | Using System Verilog files in your Project |
| Page length (in bytes) | 461 |
| Namespace ID | 0 |
| Page ID | 106 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | Cnel711 (talk | contribs) |
| Date of page creation | 22:51, 19 September 2012 |
| Latest editor | Cnel711 (talk | contribs) |
| Date of latest edit | 05:04, 20 September 2012 |
| Total number of edits | 3 |
| Total number of distinct authors | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |