File:Vhd2v isnt.txt: Revision history

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12 February 2013

  • curprev 00:1400:14, 12 February 2013‎ Ogamal talk contribs‎ 183 bytes +183‎ Simple script to read a VHDL module and generate code to instantiate it in Verilog NOTE: change script name to "vhd2v_inst.py" first then run as: "python vhd2v_inst.py <filename.vhd>"
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