Using System Verilog files in your Project - Revision history

Cnel711 at 05:04, 20 September 2012

2012-09-20T05:04:42Z

← Older revision		Revision as of 05:04, 20 September 2012
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	System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently)~~. XST (simulator) does not support System Verilog~~.		System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently).

	You'll need to add a few flags to the compilers to support System Verilog. Open the main project make file (Makefile.include) and add:		You'll need to add a few flags to the compilers to support System Verilog. Open the main project make file (Makefile.include) and add:

Cnel711 at 05:04, 20 September 2012

2012-09-20T05:04:13Z

← Older revision		Revision as of 05:04, 20 September 2012
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	<nowiki>		<nowiki>
	VERILOG_COMPILE_OPTIONS += -mfcu -sv</nowiki>		VERILOG_COMPILE_OPTIONS += -mfcu -sv</nowiki>

			Unfortunately, XST (Xilinx Synthesis Tool for creating bitfiles) won't support System Verilog until a (ever increasing) newer version. 3rd party ($$$) tools are required.

Cnel711: New page: System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently). XST (simulator) does not support System Verilog. You'll need to add a few flags to the compi...

2012-09-19T22:51:01Z

New page: System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently). XST (simulator) does not support System Verilog. You'll need to add a few flags to the compi...

New page

System Verilog constructs are supported with ModelSim 6.1+ (we use ModelSim 10.1c currently). XST (simulator) does not support System Verilog.

You'll need to add a few flags to the compilers to support System Verilog. Open the main project make file (Makefile.include) and add:

<nowiki>
VERILOG_COMPILE_OPTIONS += -mfcu -sv</nowiki>