Adding VHDL Files to a Project - Revision history

Cnel711: /* Instantiation in Verilog */

2013-02-18T18:11:51Z

Instantiation in Verilog

← Older revision		Revision as of 18:11, 18 February 2013
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	*It will look exactly like any other module instantiation in Verilog.		*It will look exactly like any other module instantiation in Verilog.
	<code> test t1(		<code>test t1(
	.in1(myInput),		.in1(myInput),
	.in2(myOtherInput),		.in2(myOtherInput),
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	*Another easier way is to use this [[Media:Vhd2v isnt.txt\|Python script to generate instantiation code in Verilog]]. Use the following command:		*Another easier way is to use this [[Media:Vhd2v isnt.txt\|Python script to generate instantiation code in Verilog]]. Use the following command:
	<code> source ~~cny_Env~~		<code>$ source cnyEnv
	$ mv ./vhd2v_inst.txt /.vhd2v_isnt.py		$ mv ./vhd2v_inst.txt /.vhd2v_isnt.py
	$ ./vhd2v_inst.py <filename></code>		$ ./vhd2v_inst.py <filename></code>

Ogamal: /* Instantiation in Verilog */

2013-02-13T08:46:52Z

Instantiation in Verilog

← Older revision		Revision as of 08:46, 13 February 2013
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	);</code>		);</code>

	*Another easier way is to use this [[Media:Vhd2v isnt.txt\|Python script]] to generate instantiation code in Verilog. Use the following command:		*Another easier way is to use this [[Media:Vhd2v isnt.txt\|Python script to generate instantiation code in Verilog]]. Use the following command:
	<code> source cny_Env		<code> source cny_Env
	$ mv ./vhd2v_inst.txt /.vhd2v_isnt.py		$ mv ./vhd2v_inst.txt /.vhd2v_isnt.py

Ogamal: /* Instantiation in Verilog */

2013-02-13T08:46:31Z

Instantiation in Verilog

← Older revision		Revision as of 08:46, 13 February 2013
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	=== Instantiation in Verilog ===		=== Instantiation in Verilog ===

	*It will look exactly like any other module instantiation in ~~verilog~~.		*It will look exactly like any other module instantiation in Verilog.
	test t1(		<code> test t1(
	.in1(myInput),		.in1(myInput),
	.in2(myOtherInput),		.in2(myOtherInput),
	.out(myOutput)		.out(myOutput)
	);		);</code>

			*Another easier way is to use this [[Media:Vhd2v isnt.txt\|Python script]] to generate instantiation code in Verilog. Use the following command:
			<code> source cny_Env
			$ mv ./vhd2v_inst.txt /.vhd2v_isnt.py
			$ ./vhd2v_inst.py <filename></code>

	=== Module With Vectors ===		=== Module With Vectors ===
	*If we change the earlier definition to look like the following		*If we change the earlier definition to look like the following

Tyler07: /* Using Your VHDL Module In The Top Level cae_pers.v File */

2013-02-02T22:38:59Z

Using Your VHDL Module In The Top Level cae_pers.v File

← Older revision		Revision as of 22:38, 2 February 2013
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	== Using Your VHDL Module In The Top Level cae_pers.v File==		== Using Your VHDL Module In The Top Level cae_pers.v File==
			=== Entity Definition ===

			entity test is
			port(
			in1 : in std_logic;
			in2 : in std_logic;
			out1: out std_logic);
			end entity;


			=== Instantiation in Verilog ===

			*It will look exactly like any other module instantiation in verilog.
			test t1(
			.in1(myInput),
			.in2(myOtherInput),
			.out(myOutput)
			);
			=== Module With Vectors ===
			*If we change the earlier definition to look like the following
			entity testWithVector is
			port(
			in1 : in std_logic_vector(63 downto 0);
			in2 : in std_logic_vector(63 downto 0);
			out1: out std_logic);
			end entity;
			*Notice that the expected input is a 64 bit wide signal path
			*Assume that you have a Verilog reg as follows
			reg [63:0] myReg;
			reg [63:0] myOtherReg;
			*Modlesim will let you directly map myReg to in1 or in2 (see below), however ISE will generally fail to compile this code, with an error about the expected size being incorrect
			test t1(
			.in1(myReg),
			.in2(myOtherReg),
			.out(myOutput)
			);
			*The easiest way around this is to map myReg to a wire, and use that in the instantiation of your VHDL module
			wire [63:0] wire_myReg;
			wire [63:0] wire_myOtherReg;
			assign wire_myReg = myReg;
			assign wire_myOtherReg = myOtherReg;

			test t1(
			.in1(wire_myReg),
			.in2(wire_myOtherReg),
			.out(myOutput)
			);

	== Include Option 1 ==		== Include Option 1 ==

Tyler07 at 22:24, 2 February 2013

2013-02-02T22:24:11Z

← Older revision		Revision as of 22:24, 2 February 2013
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	== Option 1 ==		== Using Your VHDL Module In The Top Level cae_pers.v File==


			== Include Option 1 ==
	Use the USER_VHDL_FILES variable in the project makefile:		Use the USER_VHDL_FILES variable in the project makefile:

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	The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.		The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

	== Option 1.1 ==		== Include Option 1.1 ==
	Use the USER_VHDL_FILES variable in the project's top level Makefile.include:		Use the USER_VHDL_FILES variable in the project's top level Makefile.include:
	USER_VHDL_FILES += ../vhdl/file.vhd		USER_VHDL_FILES += ../vhdl/file.vhd
	*Still use the ../ because this path will get included in the lower level directories, and will still expect a relative path.		*Still use the ../ because this path will get included in the lower level directories, and the makefile there will still expect a relative path.

	== Option 2 ==		== Include Option 2 ==
	Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:		Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

Tyler07: /* Option 1 */

2013-02-02T22:20:42Z

Option 1

← Older revision		Revision as of 22:20, 2 February 2013
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	The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.		The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

			== Option 1.1 ==
			Use the USER_VHDL_FILES variable in the project's top level Makefile.include:
			USER_VHDL_FILES += ../vhdl/file.vhd
			*Still use the ../ because this path will get included in the lower level directories, and will still expect a relative path.

	== Option 2 ==		== Option 2 ==
	Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:		Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

Cnel711 at 19:09, 25 February 2012

2012-02-25T19:09:43Z

← Older revision		Revision as of 19:09, 25 February 2012
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	~~Here's an e-mail Dr. Jones sent~~:		== Option 1 ==
	~~<nowiki>~~		Use the USER_VHDL_FILES variable in the project makefile:
	~~Here is some information Convey sent me with respect to adding VHDL files to you projects.~~

	~~1) Probably the easiest option is to use the~~ USER_VHDL_FILES ~~variable in the project makefile:~~		USER_VHDL_FILES += file1.vhd file2.vhd

	~~USER_VHDL_FILES += file1~~.~~vhd file2~~.~~vhd~~		The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

	The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.		== Option 2 ==
			Create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:
	~~2) You can also create~~ site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

	CNY_PDK_USER_DIRECTORY		CNY_PDK_USER_DIRECTORY
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	This is a good place to set which simulator you use, set up signal tracing, etc.		This is a good place to set which simulator you use, set up signal tracing, etc.

	Other information: There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.		== Other information ==
			There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.
	~~</nowiki>~~

Cnel711: New page: Here's an e-mail Dr. Jones sent: Here is some information Convey sent me with respect to adding VHDL files to you projects. 1) Probably the easiest option is to use the USER_VH...

2012-02-25T19:07:26Z

New page: Here's an e-mail Dr. Jones sent: <nowiki> Here is some information Convey sent me with respect to adding VHDL files to you projects. 1) Probably the easiest option is to use the USER_VH...

New page

Here's an e-mail Dr. Jones sent:
<nowiki>
Here is some information Convey sent me with respect to adding VHDL files to you projects.

1) Probably the easiest option is to use the USER_VHDL_FILES variable in the project makefile:

USER_VHDL_FILES += file1.vhd file2.vhd

The PDK makefile automatically compiles your VHDL files for simulation and includes them in the Xilinx project file for synthesis. Note that compile order is important with VHDL, so you should list the files in the appropriate order you want them compiled.

2) You can also create site and/or user directories that include your own makefile. The PDK automatically searches these directories for a file called "Makefile.cnypdk" and includes that in the default makefile:

CNY_PDK_USER_DIRECTORY
CNY_PDK_SITE_DIRECTORY

This is a good place to set which simulator you use, set up signal tracing, etc.

Other information: There are also several variables in the makefile that allow you to create dependencies for your own make flow. For example, the variable USER_SIM_DEPENDENCIES is listed as a dependency for the simulation, so if you want to run your own compile step before running the simulation, you can set that variable and the dependency will cause it to run that step at the right time. Others are USER_COMPILE_DEPENDENCIES and USER_PHYS_DEPENDENCIES, which is a dependency of the synthesis target.

</nowiki>