View source for Using the Write-Complete Interface

There's an optional (advanced) interface for indicating when a write completes (along with the ability to send 17 bits of write-complete control data with the write request in order to ID the requests).  Use of the interface means the write flush interface is not available.

To enable, edit the main project makefile to set the appropriate environment variable: 
export MC_WR_CMP_IF = 1

The ports to the cae_pers module must be modified; the scripts that compile verilog for both the hardware simulator and for building a bitfile will define "MC_WR_CMP_IF" inside of "pdk_fpga_defines.vh".  

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// Top of file (already included)
`include "pdk_fpga_defines.vh"

// ...

// Part of the cae_pers module port declaration
`ifdef MC_WR_CMP_IF
   output [16:0] mc0_req_wrctl_e, mc0_req_wrctl_o,
   output mc0_wr_rsp_stall_e, mc0_wr_rsp_stall_o,
   input mc0_rsp_wrcmp_e, mc0_rsp_wrcmp_o,
   input [16:0] mc0_rsp_wrctl_e, mc0_rsp_wrctl_o,
   output [16:0] mc1_req_wrctl_e, mc1_req_wrctl_o,
   output mc1_wr_rsp_stall_e, mc1_wr_rsp_stall_o,
   input mc1_rsp_wrcmp_e, mc1_rsp_wrcmp_o,
   input [16:0] mc1_rsp_wrctl_e, mc1_rsp_wrctl_o,
   output [16:0] mc2_req_wrctl_e, mc2_req_wrctl_o,
   output mc2_wr_rsp_stall_e, mc2_wr_rsp_stall_o,
   input mc2_rsp_wrcmp_e, mc2_rsp_wrcmp_o,
   input [16:0] mc2_rsp_wrctl_e, mc2_rsp_wrctl_o,
   output [16:0] mc3_req_wrctl_e, mc3_req_wrctl_o,
   output mc3_wr_rsp_stall_e, mc3_wr_rsp_stall_o,
   input mc3_rsp_wrcmp_e, mc3_rsp_wrcmp_o,
   input [16:0] mc3_rsp_wrctl_e, mc3_rsp_wrctl_o,
   output [16:0] mc4_req_wrctl_e, mc4_req_wrctl_o,
   output mc4_wr_rsp_stall_e, mc4_wr_rsp_stall_o,
   input mc4_rsp_wrcmp_e, mc4_rsp_wrcmp_o,
   input [16:0] mc4_rsp_wrctl_e, mc4_rsp_wrctl_o,
   output [16:0] mc5_req_wrctl_e, mc5_req_wrctl_o,
   output mc5_wr_rsp_stall_e, mc5_wr_rsp_stall_o,
   input mc5_rsp_wrcmp_e, mc5_rsp_wrcmp_o,
   input [16:0] mc5_rsp_wrctl_e, mc5_rsp_wrctl_o,
   output [16:0] mc6_req_wrctl_e, mc6_req_wrctl_o,
   output mc6_wr_rsp_stall_e, mc6_wr_rsp_stall_o,
   input mc6_rsp_wrcmp_e, mc6_rsp_wrcmp_o,
   input [16:0] mc6_rsp_wrctl_e, mc6_rsp_wrctl_o,
   output [16:0] mc7_req_wrctl_e, mc7_req_wrctl_o,
   output mc7_wr_rsp_stall_e, mc7_wr_rsp_stall_o,
   input mc7_rsp_wrcmp_e, mc7_rsp_wrcmp_o,
   input [16:0] mc7_rsp_wrctl_e, mc7_rsp_wrctl_o,
`else
   output		mc0_req_flush_e, mc0_req_flush_o,
   input		mc0_rsp_flush_cmplt_e, mc0_rsp_flush_cmplt_o,
   output		mc1_req_flush_e, mc1_req_flush_o,
   input		mc1_rsp_flush_cmplt_e, mc1_rsp_flush_cmplt_o,
   output		mc2_req_flush_e, mc2_req_flush_o,
   input		mc2_rsp_flush_cmplt_e, mc2_rsp_flush_cmplt_o,
   output		mc3_req_flush_e, mc3_req_flush_o,
   input		mc3_rsp_flush_cmplt_e, mc3_rsp_flush_cmplt_o,
   output		mc4_req_flush_e, mc4_req_flush_o,
   input		mc4_rsp_flush_cmplt_e, mc4_rsp_flush_cmplt_o,
   output		mc5_req_flush_e, mc5_req_flush_o,
   input		mc5_rsp_flush_cmplt_e, mc5_rsp_flush_cmplt_o,
   output		mc6_req_flush_e, mc6_req_flush_o,
   input		mc6_rsp_flush_cmplt_e, mc6_rsp_flush_cmplt_o,
   output		mc7_req_flush_e, mc7_req_flush_o,
   input		mc7_rsp_flush_cmplt_e, mc7_rsp_flush_cmplt_o,
`endif
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