Using the Memory Controller Interface

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Memory Controller Interface functionality

  • Each of the Convey application engines are connected to 8 MCs (Memory Controllers) through 300MHz DDR interface.
  • Each of the 8 MC interfaces consists of two 150MHz ports (odd port and even port). So, the MC interface contains a total of 16 port.
  • The data from the two even and odd ports are multiplexed onto the same 300 MHz channel in the MC interface.
  • Each of the even and odd ports has its request signals and response signals.
  • Refer to section 9.3.3.1 in the PDK reference manual for further information.

Memory Controller Interface Signals

The 4th MC interface of the 8 MC interfaces has the signals shown in the table below. There exist MC interfaces for n = 0 to 7. Also, you can notice that the signals are the same for the even and odd port. However, the signals for the even port use the suffix _e and the signals for the odd port use the suffix _o

Even Port Odd Port
mc4_req_ld_e mc4_req_ld_o
mc4_req_st_e mc4_req_st_o
mc4_req_size_e<1:0> mc4_req_size_o<1:0>
mc4_req_vadr_e<47:0> mc4_req_vadr_o<47:0>
mc4_req_wrd_rdctl_e<63:0> mc4_req_wrd_rdctl_o<63:0>
mc4_req_flush_e mc4_req_flush_o
mc4_rd_rq_stall_e mc4_rd_rq_stall_o
mc4_wr_rq_stall_e mc4_wr_rq_stall_o
mc4_rsp_push_e mc4_rsp_push_o
mc4_rsp_stall_e mc4_rsp_stall_o
mc4_rsp_data_e<63:0> mc4_rsp_data_o<63:0>
mc4_rsp_rdctl_e<31:0> mc4_rsp_rdctl_o<31:0>
mc4_rsp_flush_cmplt_e mc4_rsp_flush_cmplt_o


Reading from Memory

  • Before requesting any read from the memory, you have to make sure that mci_rd_rq_stall_* = '0', where i is the MC interface port number (could be from 0 to 7).
  • To request a read from memory, you have to assert the signal mci_req_ld_* and put the address of the data you want to read on the port mci_req_vadr_*.
  • The mci_req_size_*<1:0> is used to indicate if you want to read a byte, word, double-word or quad-word (i.e. 0x0 for byte, and 0x3 for quad-word).
  • You can get requested data from the mci_rsp_data_*<63:0> bus when the signal mci_rsp_push_* is asserted.
  • The lower 32 bits of mci_req_wrd_rdctl_*<63:0> will be returned as mci_rsp_rdctl_o<31:0>. You should set it while requesting a read and check it in the response to identify your request.

Writing to Memory

  • Before requesting any write to the memory, you have to make sure that mci_wr_rq_stall_* = '0'.
  • To request a write to memory, you have to assert the signal mci_req_st_* and put the address of the data you want to write to on the port mci_req_vadr_*.
  • The mci_req_size_*<1:0> is used to indicate the size as in the read scenario above.
  • The data you want to write should goes on mci_req_wrd_rdctl_*<63:0> bus.

References