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	<id>https://wikis.ece.iastate.edu/cpre584/api.php?action=feedcontributions&amp;feedformat=atom&amp;user=Xinying</id>
	<title>Cpre584 - User contributions [en]</title>
	<link rel="self" type="application/atom+xml" href="https://wikis.ece.iastate.edu/cpre584/api.php?action=feedcontributions&amp;feedformat=atom&amp;user=Xinying"/>
	<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Special:Contributions/Xinying"/>
	<updated>2026-09-05T05:01:45Z</updated>
	<subtitle>User contributions</subtitle>
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	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=909</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=909"/>
		<updated>2013-03-12T23:26:34Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Wiki Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
== References ==&lt;br /&gt;
* [http://i.cs.hku.hk/~alse/hkubrg/projects/idba/ IDBA - A Practical Iterative de Bruijn Graph De Novo Assembler]&lt;br /&gt;
&lt;br /&gt;
== Wiki Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  week 1&lt;br /&gt;
::*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
::*  Weekly presentation slides [[Media:week1slides.pptx]]&lt;br /&gt;
:*  week 2&lt;br /&gt;
::*  A Sparse Matrix Personality for the Convey HC-1 [http://ieeexplore.ieee.org/xpl/login.jsp?tp=&amp;amp;arnumber=5771239&amp;amp;url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5771239]&lt;br /&gt;
:*  week 3&lt;br /&gt;
::* Translate verilog version adder file to vhdl code.&lt;br /&gt;
::* Discuss the implementation of QR application on convey system&lt;br /&gt;
::* Cordic Algorithm Implementations on FPGA [http://cutler.eecs.berkeley.edu/classes/ee225c/Papers/cordic.pdf]&lt;br /&gt;
:*  week 4&lt;br /&gt;
::* Convey computing with bioinformatics applications [http://hpcsociety.org/Resources/Documents/121212Kirby-CONVEY-SHPCP_121212.pdf]&lt;br /&gt;
:*  week 5&lt;br /&gt;
::* Tutorial for COREGEN [http://homepages.cae.wisc.edu/~ece554/website/Xilinx/Coregen_user_guide.pdf]&lt;br /&gt;
:*  week 6&lt;br /&gt;
::* GPU-Euler: Sequence Assembly using GPGPU[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&amp;amp;arnumber=6062988]&lt;br /&gt;
:*  week 7&lt;br /&gt;
::* Genome assembly [http://www.csc.kth.se/utbildning/kth/kurser/DD2399/omsys10/lectures/genomeassembly.pdf]&lt;br /&gt;
* Qilin Li&lt;br /&gt;
:*  week 1&lt;br /&gt;
::*  Introduction to Compilers for Convey [http://www.conveycomputer.com/files/3913/5085/4426/Compiler_Data_Sheet.pdf]&lt;br /&gt;
::*  GPGPU Programming on example of CUDA [http://panoramix.ift.uni.wroc.pl/~maq/cuda/prezentacja-cuda-eng.pdf]&lt;br /&gt;
::*  Parallel Programming in CUDA C [http://developer.download.nvidia.com/books/cuda-by-example/cuda-by-example-sample.pdf]&lt;br /&gt;
:*  week 2&lt;br /&gt;
::*  [http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/ A Simple Makefile Tutorial]&lt;br /&gt;
:*  week 3&lt;br /&gt;
::*  [http://newbiedoc.sourceforge.net/text_editing/vim.html#MODES-CL A Simple VIM Tutorial]&lt;br /&gt;
:*  week 4&lt;br /&gt;
::* [[Media:ConveySystemAdministrationGuide.pdf | Convey System Administration Guide]]&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
::*  CUDA Global Memory Usage &amp;amp; Strategy. [http://developer.download.nvidia.com/CUDA/training/cuda_webinars_GlobalMemory.pdf]&lt;br /&gt;
::*  CUDA C++ code samples.[http://docs.nvidia.com/cuda/cuda-samples/index.html]&lt;br /&gt;
:* make-up for week 2&lt;br /&gt;
::* QR ecomposition on GPUs[http://dl.acm.org/citation.cfm?id=1513904]&lt;br /&gt;
::* Introduction to Householder algorithm in QR decomposition application[http://math.fullerton.edu/mathews/n2003/householdermod.html]&lt;br /&gt;
:* make-up for week 3&lt;br /&gt;
::* CUDA Memory Model[https://www.google.com/url?sa=t&amp;amp;rct=j&amp;amp;q=&amp;amp;esrc=s&amp;amp;source=web&amp;amp;cd=7&amp;amp;cad=rja&amp;amp;ved=0CEoQFjAG&amp;amp;url=https%3A%2F%2Fhub.vscse.org%2Fsite%2Fresources%2F2010%2F06%2F00048%2FCUDA_04.pdf&amp;amp;ei=_dwZUY73NKji2gWqo4GYDQ&amp;amp;usg=AFQjCNGgxpCFWYepx6v32fTHNyRI1pOOtA&amp;amp;sig2=6TW0elRmtCKW3i_fAqAT_g&amp;amp;bvm=bv.42261806,d.b2I]&lt;br /&gt;
::* CUBLAS Library Usage Reference[https://www.docs.nvidia.com/cuda/pdf/CUDA_CUBLAS_Users_Guide.pdf]&lt;br /&gt;
:* week 4&lt;br /&gt;
::* system Verilog tutorial[http://www.asic-world.com/systemverilog/tutorial.html]&lt;br /&gt;
:* week 5&lt;br /&gt;
::* most commonly used CUDA wiki website[https://developer.nvidia.com/category/zone/cuda-zone]&lt;br /&gt;
::* Nvidia GPU versions and corresponding compute capability[http://en.wikipedia.org/wiki/CUDA#Version_features_and_specifications]&lt;br /&gt;
::* methods to check CUDA memory constraints in terms of different GPU versions[http://3dgep.com/?p=1913]&lt;br /&gt;
:* week 6&lt;br /&gt;
::* open source software lists for genome alignment and assembly[http://seqanswers.com/wiki/Software/list].&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=894</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=894"/>
		<updated>2013-02-19T22:44:59Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Wiki Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Wiki Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  week 1&lt;br /&gt;
::*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
::*  Weekly presentation slides [[Media:week1slides.pptx]]&lt;br /&gt;
:*  week 2&lt;br /&gt;
::*  A Sparse Matrix Personality for the Convey HC-1 [http://ieeexplore.ieee.org/xpl/login.jsp?tp=&amp;amp;arnumber=5771239&amp;amp;url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5771239]&lt;br /&gt;
:*  week 3&lt;br /&gt;
::* Translate verilog version adder file to vhdl code.&lt;br /&gt;
::* Discuss the implementation of QR application on convey system&lt;br /&gt;
::* Cordic Algorithm Implementations on FPGA [http://cutler.eecs.berkeley.edu/classes/ee225c/Papers/cordic.pdf]&lt;br /&gt;
:*  week 4&lt;br /&gt;
::* Convey computing with bioinformatics applications [http://hpcsociety.org/Resources/Documents/121212Kirby-CONVEY-SHPCP_121212.pdf]&lt;br /&gt;
:*  week 5&lt;br /&gt;
::* Tutorial for COREGEN [http://homepages.cae.wisc.edu/~ece554/website/Xilinx/Coregen_user_guide.pdf]&lt;br /&gt;
* Qilin Li&lt;br /&gt;
:*  week 1&lt;br /&gt;
::*  Introduction to Compilers for Convey [http://www.conveycomputer.com/files/3913/5085/4426/Compiler_Data_Sheet.pdf]&lt;br /&gt;
::*  GPGPU Programming on example of CUDA [http://panoramix.ift.uni.wroc.pl/~maq/cuda/prezentacja-cuda-eng.pdf]&lt;br /&gt;
::*  Parallel Programming in CUDA C [http://developer.download.nvidia.com/books/cuda-by-example/cuda-by-example-sample.pdf]&lt;br /&gt;
:*  week 2&lt;br /&gt;
::*  [http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/ A Simple Makefile Tutorial]&lt;br /&gt;
:*  week 3&lt;br /&gt;
::*  [http://newbiedoc.sourceforge.net/text_editing/vim.html#MODES-CL A Simple VIM Tutorial]&lt;br /&gt;
:*  week 4&lt;br /&gt;
::* [[Media:ConveySystemAdministrationGuide.pdf | Convey System Administration Guide]]&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
::*  CUDA Global Memory Usage &amp;amp; Strategy. [http://developer.download.nvidia.com/CUDA/training/cuda_webinars_GlobalMemory.pdf]&lt;br /&gt;
::*  CUDA C++ code samples.[http://docs.nvidia.com/cuda/cuda-samples/index.html]&lt;br /&gt;
:* make-up for week 2&lt;br /&gt;
::* QR ecomposition on GPUs[http://dl.acm.org/citation.cfm?id=1513904]&lt;br /&gt;
::* Introduction to Householder algorithm in QR decomposition application[http://math.fullerton.edu/mathews/n2003/householdermod.html]&lt;br /&gt;
:* make-up for week 3&lt;br /&gt;
::* CUDA Memory Model[https://www.google.com/url?sa=t&amp;amp;rct=j&amp;amp;q=&amp;amp;esrc=s&amp;amp;source=web&amp;amp;cd=7&amp;amp;cad=rja&amp;amp;ved=0CEoQFjAG&amp;amp;url=https%3A%2F%2Fhub.vscse.org%2Fsite%2Fresources%2F2010%2F06%2F00048%2FCUDA_04.pdf&amp;amp;ei=_dwZUY73NKji2gWqo4GYDQ&amp;amp;usg=AFQjCNGgxpCFWYepx6v32fTHNyRI1pOOtA&amp;amp;sig2=6TW0elRmtCKW3i_fAqAT_g&amp;amp;bvm=bv.42261806,d.b2I]&lt;br /&gt;
::* CUBLAS Library Usage Reference[https://www.docs.nvidia.com/cuda/pdf/CUDA_CUBLAS_Users_Guide.pdf]&lt;br /&gt;
:* week 4&lt;br /&gt;
::* system Verilog tutorial[http://www.asic-world.com/systemverilog/tutorial.html]&lt;br /&gt;
:* week 5&lt;br /&gt;
::* most commonly used CUDA wiki website[https://developer.nvidia.com/category/zone/cuda-zone]&lt;br /&gt;
::* Nvidia GPU versions and corresponding compute capability[http://en.wikipedia.org/wiki/CUDA#Version_features_and_specifications]&lt;br /&gt;
::* methods to check CUDA memory constraints in terms of different GPU versions[http://3dgep.com/?p=1913]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=880</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=880"/>
		<updated>2013-02-13T07:11:59Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Wiki Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Wiki Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  week 1&lt;br /&gt;
::*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
::*  Weekly presentation slides [[Media:week1slides.pptx]]&lt;br /&gt;
:*  week 2&lt;br /&gt;
::*  A Sparse Matrix Personality for the Convey HC-1 [http://ieeexplore.ieee.org/xpl/login.jsp?tp=&amp;amp;arnumber=5771239&amp;amp;url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5771239]&lt;br /&gt;
:*  week 3&lt;br /&gt;
::* Translate verilog version adder file to vhdl code.&lt;br /&gt;
::* Discuss the implementation of QR application on convey system&lt;br /&gt;
::* Cordic Algorithm Implementations on FPGA [http://cutler.eecs.berkeley.edu/classes/ee225c/Papers/cordic.pdf]&lt;br /&gt;
:*  week 4&lt;br /&gt;
::* Convey computing with bioinformatics applications [http://hpcsociety.org/Resources/Documents/121212Kirby-CONVEY-SHPCP_121212.pdf]&lt;br /&gt;
* Qilin Li&lt;br /&gt;
:*  week 1&lt;br /&gt;
::*  Introduction to Compilers for Convey [http://www.conveycomputer.com/files/3913/5085/4426/Compiler_Data_Sheet.pdf]&lt;br /&gt;
::*  GPGPU Programming on example of CUDA [http://panoramix.ift.uni.wroc.pl/~maq/cuda/prezentacja-cuda-eng.pdf]&lt;br /&gt;
::*  Parallel Programming in CUDA C [http://developer.download.nvidia.com/books/cuda-by-example/cuda-by-example-sample.pdf]&lt;br /&gt;
:*  week 2&lt;br /&gt;
::*  [http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/ A Simple Makefile Tutorial]&lt;br /&gt;
:*  week 3&lt;br /&gt;
::*  [http://newbiedoc.sourceforge.net/text_editing/vim.html#MODES-CL A Simple VIM Tutorial]&lt;br /&gt;
:*  week 4&lt;br /&gt;
::* [[Media:ConveySystemAdministrationGuide.pdf | Convey System Administration Guide]]&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
::*  CUDA Global Memory Usage &amp;amp; Strategy. [http://developer.download.nvidia.com/CUDA/training/cuda_webinars_GlobalMemory.pdf]&lt;br /&gt;
::*  CUDA C++ code samples.[http://docs.nvidia.com/cuda/cuda-samples/index.html]&lt;br /&gt;
:* make-up for week 2&lt;br /&gt;
::* QR ecomposition on GPUs[http://dl.acm.org/citation.cfm?id=1513904]&lt;br /&gt;
::* Introduction to Householder algorithm in QR decomposition application[http://math.fullerton.edu/mathews/n2003/householdermod.html]&lt;br /&gt;
:* make-up for week 3&lt;br /&gt;
::* CUDA Memory Model[https://www.google.com/url?sa=t&amp;amp;rct=j&amp;amp;q=&amp;amp;esrc=s&amp;amp;source=web&amp;amp;cd=7&amp;amp;cad=rja&amp;amp;ved=0CEoQFjAG&amp;amp;url=https%3A%2F%2Fhub.vscse.org%2Fsite%2Fresources%2F2010%2F06%2F00048%2FCUDA_04.pdf&amp;amp;ei=_dwZUY73NKji2gWqo4GYDQ&amp;amp;usg=AFQjCNGgxpCFWYepx6v32fTHNyRI1pOOtA&amp;amp;sig2=6TW0elRmtCKW3i_fAqAT_g&amp;amp;bvm=bv.42261806,d.b2I]&lt;br /&gt;
::* CUBLAS Library Usage Reference[https://www.docs.nvidia.com/cuda/pdf/CUDA_CUBLAS_Users_Guide.pdf]&lt;br /&gt;
:* week 4&lt;br /&gt;
::* system Verilog tutorial[http://www.asic-world.com/systemverilog/tutorial.html]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=808</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=808"/>
		<updated>2013-02-05T21:49:32Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Wiki Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Wiki Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  week 1&lt;br /&gt;
::*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
::*  Weekly presentation slides [[Media:week1slides.pptx]]&lt;br /&gt;
:*  week 2&lt;br /&gt;
::*  A Sparse Matrix Personality for the Convey HC-1 [http://ieeexplore.ieee.org/xpl/login.jsp?tp=&amp;amp;arnumber=5771239&amp;amp;url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5771239]&lt;br /&gt;
:*  week 3&lt;br /&gt;
::* Translate verilog version adder file to vhdl code.&lt;br /&gt;
::* Discuss the implementation of QR application on convey system&lt;br /&gt;
::* Cordic Algorithm Implementations on FPGA [http://cutler.eecs.berkeley.edu/classes/ee225c/Papers/cordic.pdf]&lt;br /&gt;
* Qilin Li&lt;br /&gt;
:*  week 1&lt;br /&gt;
::*  Introduction to Compilers for Convey [http://www.conveycomputer.com/files/3913/5085/4426/Compiler_Data_Sheet.pdf]&lt;br /&gt;
::*  GPGPU Programming on example of CUDA [http://panoramix.ift.uni.wroc.pl/~maq/cuda/prezentacja-cuda-eng.pdf]&lt;br /&gt;
::*  Parallel Programming in CUDA C [http://developer.download.nvidia.com/books/cuda-by-example/cuda-by-example-sample.pdf]&lt;br /&gt;
:*  week 2&lt;br /&gt;
::*  [http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/ A Simple Makefile Tutorial]&lt;br /&gt;
:*  week 3&lt;br /&gt;
::*  [http://newbiedoc.sourceforge.net/text_editing/vim.html#MODES-CL A Simple VIM Tutorial]&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
:*  CUDA Global Memory Usage &amp;amp; Strategy. [http://developer.download.nvidia.com/CUDA/training/cuda_webinars_GlobalMemory.pdf]&lt;br /&gt;
:*  CUDA C++ code samples.[http://docs.nvidia.com/cuda/cuda-samples/index.html]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=756</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=756"/>
		<updated>2013-01-29T04:36:05Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Wiki Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Wiki Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  week 1&lt;br /&gt;
::*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
::*  Weekly presentation slides [[Media:week1slides.pptx]]&lt;br /&gt;
:*  week 2&lt;br /&gt;
::*  A Sparse Matrix Personality for the Convey HC-1 [http://ieeexplore.ieee.org/xpl/login.jsp?tp=&amp;amp;arnumber=5771239&amp;amp;url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5771239]&lt;br /&gt;
* Qilin Li&lt;br /&gt;
:*  Introduction to Compilers for Convey [http://www.conveycomputer.com/files/3913/5085/4426/Compiler_Data_Sheet.pdf]&lt;br /&gt;
:*  GPGPU Programming on example of CUDA [http://panoramix.ift.uni.wroc.pl/~maq/cuda/prezentacja-cuda-eng.pdf]&lt;br /&gt;
:*  Parallel Programming in CUDA C [http://developer.download.nvidia.com/books/cuda-by-example/cuda-by-example-sample.pdf]&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
:*  CUDA Global Memory Usage &amp;amp; Strategy. [http://developer.download.nvidia.com/CUDA/training/cuda_webinars_GlobalMemory.pdf]&lt;br /&gt;
:*  CUDA C++ code samples.[http://docs.nvidia.com/cuda/cuda-samples/index.html]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=747</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=747"/>
		<updated>2013-01-22T22:39:40Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Wiki Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Wiki Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
:*  Weekly presentation slides [[Media:week1slides.pptx]]&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
:*  CUDA Global Memory Usage &amp;amp; Strategy. [http://developer.download.nvidia.com/CUDA/training/cuda_webinars_GlobalMemory.pdf]&lt;br /&gt;
:*  CUDA C++ code samples.[http://docs.nvidia.com/cuda/cuda-samples/index.html]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Main_Page&amp;diff=746</id>
		<title>Main Page</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Main_Page&amp;diff=746"/>
		<updated>2013-01-22T22:37:36Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Helpful Guides */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Articles ==&lt;br /&gt;
=== Convey HC-1 Tutorials ===&lt;br /&gt;
* [[Connecting to convey-1.ece.iastate.edu]]&lt;br /&gt;
* [[Convey environment setup|Setting Up Environment Variables on Convey&#039;s HC-1]]&lt;br /&gt;
* [[Running the Vector Adder Example Application]]&lt;br /&gt;
* Convey pdk tutorial: [[image:ConveyTutorial1.pdf]] (uses newCnyProject script)&lt;br /&gt;
* [[Analyze the Simpleton Basic App]]&lt;br /&gt;
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]&lt;br /&gt;
* [[Using a Custom Bitfile in C Code]]&lt;br /&gt;
* [[Adding VHDL Files to a Project]]&lt;br /&gt;
* [[The Verilog Hardware Interface for CAE]]&lt;br /&gt;
* [[Using ISE&#039;s Core Generator to build FIFOs and other IP cores]]&lt;br /&gt;
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]&lt;br /&gt;
* [[Using the Write-Complete Interface]]&lt;br /&gt;
* [[Using the Timing Analyzer]]&lt;br /&gt;
&lt;br /&gt;
* [[Using SPAT]]&lt;br /&gt;
* [[Using GPROF]]&lt;br /&gt;
* [[Convey vector example | Example of Loop Unrolling using FPGA]]&lt;br /&gt;
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]&lt;br /&gt;
&lt;br /&gt;
== Reference Manuals ==&lt;br /&gt;
=== Convey ===&lt;br /&gt;
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)&lt;br /&gt;
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)&lt;br /&gt;
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]&lt;br /&gt;
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]&lt;br /&gt;
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]&lt;br /&gt;
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]&lt;br /&gt;
&lt;br /&gt;
The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey&#039;s Support Site]&lt;br /&gt;
&lt;br /&gt;
=== CUDA ===&lt;br /&gt;
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]&lt;br /&gt;
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]&lt;br /&gt;
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]&lt;br /&gt;
&lt;br /&gt;
==Links==&lt;br /&gt;
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs&lt;br /&gt;
* [http://memocode.irisa.fr MemoCODE 2012]&lt;br /&gt;
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]&lt;br /&gt;
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]&lt;br /&gt;
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]&lt;br /&gt;
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]&lt;br /&gt;
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]&lt;br /&gt;
&lt;br /&gt;
* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]&lt;br /&gt;
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]&lt;br /&gt;
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]&lt;br /&gt;
&lt;br /&gt;
=== Other Articles ===&lt;br /&gt;
* [[Assignment|Assignments]]&lt;br /&gt;
* [[A quick start on CUDA]]&lt;br /&gt;
&lt;br /&gt;
== Helpful Guides ==&lt;br /&gt;
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]&lt;br /&gt;
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]&lt;br /&gt;
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf &amp;quot;The Shock and Awe&amp;quot; VHDL Tutorial]&lt;br /&gt;
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]&lt;br /&gt;
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]&lt;br /&gt;
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]&lt;br /&gt;
* [[Media:Modelsim_pe_user_10.0d.pdf | Modelsim Users Guide]]&lt;br /&gt;
* [[Useful Modelsim Commands]]&lt;br /&gt;
* [http://sn0v.wordpress.com/2012/12/07/installing-cuda-5-on-ubuntu-12-04/ Installing CUDA on Ubuntu]&lt;br /&gt;
* [http://graphics.stanford.edu/~mhouston/public_talks/R520-mhouston.pdf General Purpose Computation on GPUs (GPGPU)]&lt;br /&gt;
*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
&lt;br /&gt;
== Readings for Memocode 2012 ==&lt;br /&gt;
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]&lt;br /&gt;
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]&lt;br /&gt;
&lt;br /&gt;
== Spring 2012 Teams ==&lt;br /&gt;
* [[Team Gryffindor]]&lt;br /&gt;
* [[Team Slytherin]]&lt;br /&gt;
* [[Team 142857]]&lt;br /&gt;
== Spring 2013 Teams ==&lt;br /&gt;
* [[Team Cyc05]]&lt;br /&gt;
* [[Team Challenger]]&lt;br /&gt;
* [[Team Blitz]]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=745</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=745"/>
		<updated>2013-01-22T22:33:54Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Wiki Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Wiki Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
:*  Weekly presentation slides[[Media:week_1_slides.ppt]]&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
:*  CUDA Global Memory Usage &amp;amp; Strategy. [http://developer.download.nvidia.com/CUDA/training/cuda_webinars_GlobalMemory.pdf]&lt;br /&gt;
:*  CUDA C++ code samples.[http://docs.nvidia.com/cuda/cuda-samples/index.html]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=744</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=744"/>
		<updated>2013-01-22T22:25:21Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Wiki Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Wiki Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
:*  Weekly presentation slides&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
:*  CUDA Global Memory Usage &amp;amp; Strategy. [http://developer.download.nvidia.com/CUDA/training/cuda_webinars_GlobalMemory.pdf]&lt;br /&gt;
:*  CUDA C++ code samples.[http://docs.nvidia.com/cuda/cuda-samples/index.html]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=734</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=734"/>
		<updated>2013-01-22T15:20:49Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Week 1 Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Wiki Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=733</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=733"/>
		<updated>2013-01-22T15:18:47Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Week 1 Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Week 1 Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=732</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=732"/>
		<updated>2013-01-22T15:17:18Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Week 1 Contributions */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Week 1 Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
:*  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=724</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=724"/>
		<updated>2013-01-22T05:11:54Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Team Members */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Week 1 Contributions ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
  Convey vector personalities offer OpenMP-like programming approach with FPGA accelerating. [http://www.fpl2012.org/Presentations/W4B2.pdf]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Main_Page&amp;diff=707</id>
		<title>Main Page</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Main_Page&amp;diff=707"/>
		<updated>2013-01-21T06:21:11Z</updated>

		<summary type="html">&lt;p&gt;Xinying: /* Spring 2013 Teams */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Articles ==&lt;br /&gt;
=== Convey HC-1 Tutorials ===&lt;br /&gt;
* [[Connecting to convey-1.ece.iastate.edu]]&lt;br /&gt;
* [[Convey environment setup|Setting Up Environment Variables on Convey&#039;s HC-1]]&lt;br /&gt;
* [[Running the Vector Adder Example Application]]&lt;br /&gt;
* Convey pdk tutorial: [[image:ConveyTutorial1.pdf]] (uses newCnyProject script)&lt;br /&gt;
* [[Analyze the Simpleton Basic App]]&lt;br /&gt;
* [[Tutorial: Creating a Custom Bitfile | Create a Custom Bitfile]]&lt;br /&gt;
* [[Using a Custom Bitfile in C Code]]&lt;br /&gt;
* [[Adding VHDL Files to a Project]]&lt;br /&gt;
* [[The Verilog Hardware Interface for CAE]]&lt;br /&gt;
* [[Using ISE&#039;s Core Generator to build FIFOs and other IP cores]]&lt;br /&gt;
* [[Running Different Bitfiles on each AE | Projects with Multiple Bitfiles]]&lt;br /&gt;
* [[Using the Write-Complete Interface]]&lt;br /&gt;
* [[Using the Timing Analyzer]]&lt;br /&gt;
&lt;br /&gt;
* [[Using SPAT]]&lt;br /&gt;
* [[Using GPROF]]&lt;br /&gt;
* [[Convey vector example | Example of Loop Unrolling using FPGA]]&lt;br /&gt;
* [[Sobel Algorithm | Speeding up Sobel Algorithm]]&lt;br /&gt;
&lt;br /&gt;
== Reference Manuals ==&lt;br /&gt;
=== Convey ===&lt;br /&gt;
* [[Media:ConveyPDKReferenceManual.pdf | Convey PDK Reference Manual (.pdf)]] (updated to V5.2; April 2012)&lt;br /&gt;
* [[Media:ConveyProgrammersGuide.pdf | Convey Programmers Guide (.pdf)]] (updated to V1.8; November 2010)&lt;br /&gt;
* [[Media:ConveyReferenceManual.pdf | Convey Reference Manual (.pdf)]]&lt;br /&gt;
* [[Media:ConveySpatUsersGuide.pdf | Convey SPAT (Simulator Performance Analysis Tool) Guide]]&lt;br /&gt;
* [[Media:Convey PDK Training.pdf | Convey PDK (.pdf)]]&lt;br /&gt;
* [[Media:Convey Overview.pdf | Convey Overview (.pdf)]]&lt;br /&gt;
&lt;br /&gt;
The newet version of these documents are available at [http://www.conveysupport.com/help/?page_id=112 Convey&#039;s Support Site]&lt;br /&gt;
&lt;br /&gt;
=== CUDA ===&lt;br /&gt;
* [[Media:CUDA_C_Programming_Guide.pdf | CUDA_C_Programming_Guide (.pdf)]]&lt;br /&gt;
* [[Media:CUDA_C_Best_Practices_Guide.pdf | CUDA_C_Best_Practices_Guide(.pdf)]]&lt;br /&gt;
* [[Media:CUDA_Memory.pdf | CUDA_Memory (.pdf)]]&lt;br /&gt;
&lt;br /&gt;
==Links==&lt;br /&gt;
* [http://www.asic-world.com www.asic-world.com] - Great Tutorials for those Learning HDLs&lt;br /&gt;
* [http://memocode.irisa.fr MemoCODE 2012]&lt;br /&gt;
** [[Media:2012-memocode-contest.pdf | MemoCODE Contest.pdf]]&lt;br /&gt;
** [http://memocode.irisa.fr/2012/2012-memocode-contest.tar.gz Reference Implementation]&lt;br /&gt;
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/technical/reference/human_g1k_v37.fasta.gz Human Reference Genome (human_g1k_v37.fasta.gz)]&lt;br /&gt;
** [ftp://ftp-trace.ncbi.nih.gov/1000genomes/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (ERR050082.filt.fastq.gz)]&lt;br /&gt;
** [http://ftp.1000genomes.ebi.ac.uk/vol1/ftp/data/NA06985/sequence_read/ERR050082.filt.fastq.gz Example Reads (Alternative Link) (ERR050082.filt.fastq.gz)]&lt;br /&gt;
&lt;br /&gt;
* [[2010 Main Page | CprE 584 2010 Wiki Main Page]]&lt;br /&gt;
* [http://class.ee.iastate.edu/cpre583/ CprE 583 Website]&lt;br /&gt;
* [http://class.ece.iastate.edu/cpre584/ CprE 584 Website]&lt;br /&gt;
&lt;br /&gt;
=== Other Articles ===&lt;br /&gt;
* [[Assignment|Assignments]]&lt;br /&gt;
* [[A quick start on CUDA]]&lt;br /&gt;
&lt;br /&gt;
== Helpful Guides ==&lt;br /&gt;
* [http://www.c7t-hdl.com/Docs/C7T_AN05_Customized_WaveView_ModelSim_ISE.pdf Modelsim and ISE]&lt;br /&gt;
* [http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf The Verilog Golden Reference]&lt;br /&gt;
* [http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf &amp;quot;The Shock and Awe&amp;quot; VHDL Tutorial]&lt;br /&gt;
* [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Simple Code Examples]&lt;br /&gt;
* [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL Primer]&lt;br /&gt;
* [http://www.kxcad.net/electronic_Xilinx_guide/mergedProjects/xsim/html/xs_p_ml_instantiation.htm Using VHDL components in Verilog]&lt;br /&gt;
&lt;br /&gt;
== Readings for Memocode 2012 ==&lt;br /&gt;
*[[Media:Brief_Bioinform-2010-Li-473-83.pdf|A survey on algorithms for sequencing]]&lt;br /&gt;
*[[Media:Gb-2009-10-3-r25.pdf|Burrows-Wheeler indexing]]&lt;br /&gt;
&lt;br /&gt;
== Spring 2012 Teams ==&lt;br /&gt;
* [[Team Gryffindor]]&lt;br /&gt;
* [[Team Slytherin]]&lt;br /&gt;
* [[Team 142857]]&lt;br /&gt;
== Spring 2013 Teams ==&lt;br /&gt;
* [[Team Cyc05]]&lt;br /&gt;
* [[Team Challenger]]&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
	<entry>
		<id>https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=706</id>
		<title>Team Challenger</title>
		<link rel="alternate" type="text/html" href="https://wikis.ece.iastate.edu/cpre584/index.php?title=Team_Challenger&amp;diff=706"/>
		<updated>2013-01-21T06:19:49Z</updated>

		<summary type="html">&lt;p&gt;Xinying: New page: == Team Members ==  * Xinying Wang * Qilin Li * Zhong Hu&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Team Members ==&lt;br /&gt;
&lt;br /&gt;
* Xinying Wang&lt;br /&gt;
* Qilin Li&lt;br /&gt;
* Zhong Hu&lt;/div&gt;</summary>
		<author><name>Xinying</name></author>
	</entry>
</feed>